MPC8308CVMADDA datasheet(74/95 Pages) NXP

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Thermal

21.3

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). This table shows the encodings for RCWL[COREPLL]. COREPLL values that are

not listed in this table should be considered as reserved.

NOTE

Core VCO frequency = core frequency

VCO divider. The VCO divider,

which is determined by RCWLR[COREPLL], must be set properly so that

the core VCO frequency is in the range of 400–800 MHz.

22 Thermal

This section describes the thermal specifications of the device.

Table 58. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk: csb_clk

Ratio1

1 For any core_clk:csb_clk ratios, the core_clk must not exceed its maximum operating frequency of 400 MHz.

VCO Divider (VCOD)2

2 Core VCO frequency = core frequency

 VCO divider. Note that VCO divider has to be set properly so that the

core VCO frequency is in the range of 400–800 MHz.

0–1

2–5

0000

PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core directly)

nnnn

nn/a

n/a

0001

01:1

0001

01:1

0001

01:1

0001

1.5:1

0001

1.5:1

0001

1.5:1

0010

02:1

0010

02:1

0010

02:1

0010

2.5:1

0010

2.5:1

0010

2.5:1

0011

03:1

0011

03:1

0011

03:1

Note:

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