ADUC7023BCPZ62I-R7 datasheet(22/98 Pages) AD

22 / 98 page

ADuC7023

Data Sheet

Rev. H | Page 22 of 98

More information relative to the model of the programmer and

the ARM7TDMI core architecture can be found in ARM7TDMI

technical and ARM architecture manuals available directly from

ARM Ltd.

INTERRUPT LATENCY

The worst-case latency for a fast interrupt request (FIQ)

consists of the following: the longest time the request can take

to pass through the synchronizer, the time for the longest

instruction to complete (the longest instruction is an LDM)

that loads all the registers including the PC, and the time for the

data abort and FIQ entry.

At the end of this time, the ARM7TDMI executes the instruc-

tion at 0x1C (FIQ interrupt vector address). The maximum

total time is 50 processor cycles, which is just under 1.2 μs in a

system using a continuous 41.78 MHz processor clock.

The maximum interrupt request (IRQ) latency calculation is

similar but must allow for the fact that FIQ has higher priority

and could delay entry into the IRQ handling routine for an

arbitrary length of time. This time can be reduced to 42 cycles if

the LDM command is not used. Some compilers have an option

to compile without using this command. Another option is to run

the part in thumb mode where the time is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is a total of

five cycles, which consist of the shortest time the request can

take through the synchronizer, plus the time to enter the

exception mode.

The ARM7TDMI always runs in ARM (32-bit) mode when in

privileged modes, for example, when executing interrupt

service routines.

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