ADUC7023BCPZ62I-R7 datasheet(46/98 Pages) AD

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ADuC7023

Data Sheet

Rev. H | Page 46 of 98

OTHER ANALOG PERIPHERALS

DAC

The ADuC7023 incorporates four, 12-bit voltage output DACs

on chip. Each DAC has a rail-to-rail voltage output buffer

capable of driving 5 kΩ/100 pF.

Each DAC has two selectable ranges: 0 V to VREF (internal band

gap 2.5 V reference) and 0 V to AVDD.

The signal range is 0 V to AVDD.

By setting RSTCFG Bit 2, the DAC output pins can retain their

state during a watchdog or software reset.

MMRs Interface

Each DAC is independently configurable through a control

the four DACs. Only DAC0CON (see Table 40) and

DAC0DAT (see Table 41) are described in detail in this section.

DACxCON Registers

Name

Address

Default Value

Access

DAC0CON

0xFFFF0600

0x00

R/W

DAC1CON

0xFFFF0608

0x00

R/W

DAC2CON

0xFFFF0610

0x00

R/W

DAC3CON

0xFFFF0618

0x00

R/W

Table 40. DAC0CON MMR Bit Designations

Bit

Value

Name

Description

Reserved.

DACBY

This bit is set to bypass the DAC

output buffer.

This bit is cleared to enable the

DAC output buffer.

DACCLK

DAC update rate.

This bit is set by the user to update

the DAC using Timer1.

This bit is cleared by the user to

update the DAC using HCLK (core

clock).

DACCLR

DAC clear bit.

This bit is set by the user to enable

normal DAC operation.

This bit is cleared by the user to

reset data register of the DAC to 0.

Reserved. This bit remains at 0.

1 to 0

DAC range bits.

Power-down mode. The DAC

output is in tristate.

Reserved.

0 V to VREF (2.5 V) range.

0 V to AVDD range.

DACxDAT Registers

Name

Address

Default Value

Access

DAC0DAT

0xFFFF0604

0x00000000

R/W

DAC1DAT

0xFFFF060C

0x00000000

R/W

DAC2DAT

0xFFFF0614

0x00000000

R/W

DAC3DAT

0xFFFF061C

0x00000000

R/W

Table 41. DAC0DAT MMR Bit Designations

Bit

Description

31 to 28

Reserved.

27 to 16

12-bit data for DAC0.

15 to 0

Reserved.

Using the DACs

The on-chip DAC architecture consists of a resistor string DAC

followed by an output buffer amplifier. The functional equivalent

is shown in Figure 32.

DAC0

VREF

AVDD

DACREF

Figure 32. DAC Structure

As illustrated in Figure 32, the reference source for each DAC

is user-selectable in software. It can be either AVDD or VREF. In

0-to-AVDD mode, the DAC output transfer function spans from

0 V to the voltage at the AVDD pin. In 0-to-VREF mode, the DAC

output transfer function spans from 0 V to the internal 2.5 V

reference, VREF.

The DAC output buffer amplifier features a true, rail-to-rail

output stage implementation. This means that when unloaded,

each output is capable of swinging to within less than 5 mV of

both AVDD and ground. Moreover, the DAC linearity specification

(when driving a 5 kΩ resistive load to ground) is guaranteed

through the full transfer function except Code 0 to Code 100,

and, in 0-to-AVDD mode only, Code 3995 to Code 4095.

Linearity degradation near ground and VDD is caused by saturation

of the output amplifier, and a general representation of its effects

(neglecting offset and gain error) is illustrated in Figure 33. The

dotted line in Figure 33 indicates the ideal transfer function, and

the solid line represents what the transfer function may look like

with endpoint nonlinearities due to saturation of the output

amplifier. Figure 33 represents a transfer function in 0-to-AVDD

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