ADUC7023BCPZ62I-R7 datasheet(25/98 Pages) AD

25 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 25 of 98

Table 10. IRQ Address Base = 0xFFFF0000

Address

Name

Byte

Access

Type

Default Value

Description

0x0000

IRQSTA

0x00000000

Active IRQ source.

0x0004

IRQSIG

Current state of all IRQ sources (enabled and disabled).

0x0008

IRQEN

R/W

0x00000000

Enabled IRQ sources.

0x000C

IRQCLR

MMR to disable IRQ sources.

0x0010

SWICFG

Software interrupt configuration MMR.

0x0014

IRQBASE

R/W

0x00000000

Base address of all vectors. Points to start of a 64-byte memory block

which can contain up to 32 pointers to separate subroutine handlers.

0x001C

IRQVEC

0x00000000

This register contains the subroutine address for the currently active

IRQ source.

0x0020

IRQP0

R/W

0x00000000

This register contains the interrupt priority setting for Interrupt Source 1

to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.

0x0024

IRQP1

R/W

0x00000000

This register contains the interrupt priority setting for Interrupt Source 8

to Interrupt Source 15.

0x0028

IRQP2

R/W

0x00000000

This register contains the interrupt priority setting for Interrupt Source 16 to

Interrupt Source 21.

0x002C

RESERVED

R/W

0x00000000

Reserved.

0x0030

IRQCONN

R/W

0x00000000

Used to enable IRQ and FIQ interrupt nesting.

0x0034

IRQCONE

R/W

0x00000000

This register configures the external interrupt sources as rising edge,

falling edge, or level triggered.

0x0038

IRQCLRE

R/W

0x00000000

Used to clear an edge level triggered interrupt source.

0x003C

IRQSTAN

R/W

0x00000000

This register indicates the priority level of an interrupt that has just

caused an interrupt exception.

0x0100

FIQSTA

0x00000000

Active FIQ source.

0x0104

FIQSIG

Current state of all FIQ sources (enabled and disabled).

0x0108

FIQEN

R/W

0x00000000

Enabled FIQ sources.

0x010C

FIQCLR

MMR to disable FIQ sources.

0x011C

FIQVEC

0x00000000

FIQ interrupt vector.

0x013C

FIQSTAN

0x00000000

This register indicates the priority level of an FIQ that has just caused an

FIQ exception.

Table 11. System Control Address Base = 0xFFFF0200

Address

Name

Byte

Access

Type

Default Value1

Description

0x0220

Remap2

R/W

0x00

Remap control register.

0x0230

RSTSTA

R/W

0x01

RSTSTA status MMR.

0x0234

RSTCLR

0x00

RSTCLR MMR for clearing RSTSTA register.

0x0248

RSTKEY1

0xXX

0x76 should be written to this register before writing to RSTCFG.

0x024C

RSTCFG

R/W

0x00

This register allows the DAC and GPIO outputs to retain state after a

watchdog or software reset.

0x0250

RSTKEY2

0xXX

0xB1 should be written to this register after writing to RSTCFG.

1 N/A means not applicable.

2 Updated by kernel.

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