ADUC7023BCPZ62I-R7 datasheet(61/98 Pages) AD

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Data Sheet

ADuC7023

Rev. H | Page 61 of 98

I2C

The ADuC7023 incorporates two I2C peripherals that may be

configured as a fully I2C-compatible I2C bus master device or as

a fully I2C bus-compatible slave device.

The two pins used for data transfer, SDA and SCL, are

configured in a wire-AND format that allows arbitration in a

multimaster system. These pins require external pull-up

resistors. Typical pull-up values are between 4.7 kΩ and 10 kΩ.

The I2C bus peripheral address in the I2C bus system is pro-

grammed by the user. This ID can be modified any time a

transfer is not in progress. The user can configure the interface

to respond to four slave addresses.

The transfer sequence of an I2C system consists of a master

device initiating a transfer by generating a start condition while

the bus is idle. The master transmits the slave device address

and the direction of the data transfer (read or/write) during the

initial address transfer. If the master does not lose arbitration

and the slave acknowledges the data, transfer is initiated. This

continues until the master issues a stop condition and the bus

becomes idle.

The I2C peripheral can only be configured as a master or slave

at any given time. The same I2C channel cannot simultaneously

support master and slave modes.

The I2C interface on the ADuC7023 includes support for

repeated start conditions. In master mode, the ADuC7023 can

be programmed to generate a repeated start. In slave mode, the

ADuC7023 recognizes repeated start conditions. In master and

slave mode, the part recognizes both 7-bit and 10-bit bus

addresses. In I2C master mode, the ADuC7023 supports

continuous reads from a single slave up to 512 bytes in a single

transfer sequence. Clock stretching can be enabled by other

devices on the bus without causing any issues with the

ADuC7023. However, the ADuC7023 cannot enable clock

stretching. In slave mode, the ADuC7023 can be programmed

to return a NACK. This allows the validation of checksum bytes

at the end of I2C transfers. Bus arbitration in master mode is

supported. Internal and external loopback modes are supported

for I2C hardware testing. In loopback mode. The transmit and

receive circuits in both master and slave mode contain 2-byte

FIFOs. Status bits are available to the user to control these

FIFOs.

CONFIGURING EXTERNAL PINS FOR I2C

FUNCTIONALITY

The I2C pins of the ADuC7023 device are P0.4 and P0.5 for

I2C0 and P0.6 and P0.7 for I2C1.

P0.4 and P0.6 are the I2C clock signals and P0.5 and P0.7 are

the I2C data signals. For instance, to configure I2C0 pins (SCL0,

SDA0), Bit 16 and Bit 20 of the GP0CON register must be set to

1 to enable I2C mode. On the other hand, to configure I2C1 pins

(SCL1, SDA1), Bit 25 and Bit 29 of the GP0CON register must

be set to 1 to enable I2C mode, as shown in the GPIO section.

I2C1 function is available at P0.6 and P0.7 on 32-lead and 36-ball

packages and available at P1.6 and P1.7 on 40-lead package.

SERIAL CLOCK GENERATION

The I2C master in the system generates the serial clock for a

transfer. The master channel can be configured to operate in

fast mode (400 kHz) or standard mode (100 kHz).

The bit rate is defined in the I2CDIV MMR as follows:

)

(

DIVL

DIVH





UCLK

CLOCK

SERIAL

where:

fUCLK is the clock before the clock divider and the clock selected

by POWCON1 Bit 4 to Bit 0.

DIVH is the high period of the clock.

DIVL is the low period of the clock.

Thus, for 100 kHz operation,

DIVH = DIVL = 0xCF

and for 400 kHz,

DIVH = 0x28, DIVL = 0x3C

The I2CDIV register corresponds to DIVH:DIVL.

I2C BUS ADDRESSES

Slave Mode

In slave mode, the registers I2CxID0, I2CxID1, I2CxID2, and

I2CxID3 contain the device IDs. The device compares the four

I2CxIDx registers to the address byte received from the bus master.

To be correctly addressed, the 7MSBs of either ID register must be

identical to that of the 7MSBs of the first received address byte.

The LSB of the ID registers (the transfer direction bit) is

ignored in the process of address recognition.

The ADuC7023 also supports 10-bit addressing mode. When

Bit 1 of I2CxSCON (ADR10EN bit) is set to 1, then one 10-bit

address is supported in slave mode and is stored in registers

I2CxID0 and I2CxID1. The 10-bit address is derived as follows:

I2CxID0[7:3] must be set to 11110b.

I2CxID0[2:1] = Address Bits[9:8].

I2CxID0[0] is the read/write bit and is not part of the I2C

address. This must be written as 0.

I2CxID0[7:0] = Address Bits[7:0].

Master Mode

In master mode, the I2CxADR0 register is programmed with

the I2C address of the device.

In 7-bit address mode, I2CxADR0[7:1] are set to the device

address. I2CxADR0[0] is the read/write bit.

In 10-bit address mode, the 10-bit address is created as follows:

I2CxADR0[7:3] must be set to 11110b.

I2CxADR0[2:1] = Address Bits[9:8].

I2CxADR1[7:0] = Address Bits[7:0].

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