ADUC7023BCPZ62I-R7 datasheet(35/98 Pages) AD

35 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 35 of 98

ADCGN Register

Name:

ADCGN

Address:

0xFFFF0530

Default value:

Factory configured

Access:

Read/write

Function:

ADCGN is a 10-bit gain calibration

ADCOF Register

Name:

ADCOF

Address:

0xFFFF0534

Default value:

Factory configured

Access:

Read/write

Function:

ADCOF is a 10-bit offset calibration

CONVERTER OPERATION

The ADC incorporates a successive approximation (SAR)

architecture involving a charge-sampled input stage. This

architecture can operate in two different modes: differential

and single-ended.

Differential Mode

The ADuC7023 contains a successive approximation ADC

based on two capacitive DACs. Figure 24 and Figure 25 show

simplified schematics of the ADC in acquisition and conversion

phase, respectively. The ADC is comprised of control logic, a

SAR, and two capacitive DACs. In Figure 24 (the acquisition

phase), SW3 is closed and SW1 and SW2 are in Position A. The

comparator is held in a balanced condition, and the sampling

capacitor arrays acquire the differential signal on the input.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

ADC0

ADC11

MUX

CHANNEL+

CHANNEL–

Figure 24. ADC Acquisition Phase

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

SW2

VREF

ADC0

ADC11

MUX

CHANNEL+

CHANNEL–

Figure 25. ADC Conversion Phase

When the ADC starts a conversion, as shown in Figure 25,

SW3 opens, and then SW1 and SW2 move to Position B. This

causes the comparator to become unbalanced. Both inputs are

disconnected once the conversion begins. The control logic

and the charge redistribution DACs are used to add and

subtract fixed amounts of charge from the sampling capacitor

arrays to bring the comparator back into a balanced condition.

When the comparator is rebalanced, the conversion is

complete. The control logic generates the ADC output code.

The output impedances of the sources driving the VIN+ and VIN–

pins must be matched; otherwise, the two inputs have different

settling times, resulting in errors.

Single-Ended Mode

In single-ended mode, SW2 is always connected internally to

ground. The VIN− pin can be floating. The input signal range on

VIN+ is 0 V to VREF.

CAPACITIVE

DAC

CAPACITIVE

DAC

CONTROL

LOGIC

COMPARATOR

SW3

SW1

ADC0

ADC11

MUX

CHANNEL+

CHANNEL–

Figure 26. ADC in Single-Ended Mode

Analog Input Structure

Figure 27 shows the equivalent circuit of the analog input

structure of the ADC. The four diodes provide ESD protection for

the analog inputs. Care must be taken to ensure that the analog

input signals never exceed the supply rails by more than 300

mV; this causes these diodes to become forward-biased and

start conducting into the substrate. These diodes can conduct

up to 10 mA without causing irreversible damage to the part.

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