ADUC7023BCPZ62I-R7 datasheet(23/98 Pages) AD

23 / 98 page

Data Sheet

ADuC7023

Rev. H | Page 23 of 98

MEMORY ORGANIZATION

The ADuC7023 incorporates two separate blocks of memory:

8 kB of SRAM and 64 kB of on-chip Flash/EE memory; 62 kB

of on-chip Flash/EE memory is available to the user, and the

remaining 2 kB are reserved for the factory configured boot

page. These two blocks are mapped as shown in Figure 16.

RESERVED

MMRs

0xFFFFFFFF

0x0008FFFF

0x00011FFF

0x0000FFFF

0x00000000

0x00010000

0x00080000

0xFFFF0000

RESERVED

FLASH/EE

(FLASH/EE OR SRAM)

REMAPPABLE MEMORY SPACE

SRAM

Figure 16. Physical Memory Map

By default, after a reset, the Flash/EE memory is mirrored at

Address 0x00000000. It is possible to remap the SRAM at

Address 0x00000000 by clearing Bit 0 of the Remap MMR.

This remap function is described in more detail in the Flash/EE

Memory section.

MEMORY ACCESS

The ARM7 core sees memory as a linear array of the 232 byte

location where the different blocks of memory are mapped as

outlined in Figure 16.

The ADuC7023 memory organizations are configured in little

endian format, which means that the least significant byte is

located in the lowest byte address, and the most significant byte

is in the highest byte address.

BIT 31

BYTE 2

BYTE 3

BYTE 1

BYTE 0

BIT 0

32 BITS

0xFFFFFFFF

0x00000004

0x00000000

Figure 17. Little Endian Format

FLASH/EE MEMORY

The total 64 kB of Flash/EE memory is organized as 32k × 16 bits;

31k × 16 bits is user space and 1 k × 16 bits is reserved for the

on-chip kernel. The page size of this Flash/EE memory is 512 bytes.

62 kilobytes of Flash/EE memory are available to the user as

code and nonvolatile data memory. There is no distinction

between data and program because ARM code shares the same

space. The real width of the Flash/EE memory is 16 bits, which

means that in ARM mode (32-bit instruction), two accesses to

the Flash/EE are necessary for each instruction fetch. It is,

therefore, recommended to use Thumb mode when executing

from Flash/EE memory for optimum access speed. The

maximum access speed for the Flash/EE memory is 41.78 MHz

in Thumb mode and 20.89 MHz in full ARM mode. More

details about Flash/EE access time are outlined later in the

Execution Time from SRAM and Flash/EE section.

SRAM

Eight kilobytes of SRAM are available to the user, organized as

2k × 32 bits, that is, two words. ARM code can run directly from

SRAM at 41.78 MHz, given that the SRAM array is configured as a

32-bit wide memory array. More details about SRAM access

time are outlined later in the Execution Time from SRAM and

Flash/EE section.

MEMORY MAPPED REGISTERS

The memory mapped register (MMR) space is mapped into the

upper two pages of the memory array and accessed by indirect

addressing through the ARM7 banked registers.

The MMR space provides an interface between the CPU and

all on-chip peripherals. All registers, except the core registers,

reside in the MMR area. All shaded locations shown in Figure 18

are unoccupied or reserved locations and should not be

accessed by user software. Table 10 to Table 23 show the full

MMR memory map.

The access time for reading from or writing to an MMR depends

on the advanced microcontroller bus architecture (AMBA) bus

used to access the peripheral. The processor has two AMBA

buses: advanced high performance bus (AHB) used for system

modules and advanced peripheral bus (APB) used for lower

performance peripheral. Access to the AHB is one cycle, and

access to the APB is two cycles. All peripherals on the ADuC7023

are on the APB except the Flash/EE memory and the GPIOs.

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