ADUC7023BCPZ62I-R7 datasheet(66/98 Pages) AD

66 / 98 page

ADuC7023

Data Sheet

Rev. H | Page 66 of 98

Bit

Name

Description

I2CGCCLR

I2C general call status and ID clear bit.

Writing a 1 to this bit clears the general call status and ID bits in the I2CxSSTA register.

This bit is cleared at all other times.

I2CHGCEN

I2C hardware general call enable. Hardware general call enable. When this bit and Bit 2 are set, and having

received a general call (Address 0x00) and a data byte, the device checks the contents of the I2CxALT against

the receive register. If the contents match, the device has received a hardware general call. This is used if a

device needs urgent attention from a master device without knowing which master it needs to turn to. This is

a broadcast message to all master devices on the bus. The ADuC7023 watches for these addresses. The device

that requires attention embeds its own address into the message. All masters listen, and the one that can

handle the device contacts its slave and acts appropriately. The LSB of the I2CxALT register should always be

written to 1, as per the I2C January 2000 bus specification.

This bit and I2CGCEN are set to enable hardware general call recognition in slave mode.

This bit is cleared to disable recognition of hardware general call commands.

I2CGCEN

I2C general call enable. This bit is set to enable the slave device to acknowledge an I2C general call, Address

0x00 (write). The device then recognizes a data bit. If it receives a 0x06 (reset and write programmable part of

the slave address by hardware) as the data byte, the I2C interface resets as per the I2C January 2000 bus

specification. This command can be used to reset an entire I2C system. If it receives a 0x04 (write programmable part

of the slave address by hardware) as the data byte, the general call interrupt status bit sets on any general call.

The user must take corrective action by reprogramming the device address.

This bit is set to allow the slave acknowledge I2C general call commands.

This bit is cleared to disable recognition of general call commands.

ADR10EN

I2C 10-bit address mode.

This bit is set to 1 to enable 10-bit address mode.

This bit is cleared to 0 to enable normal address mode.

I2CSEN

I2C slave enable bit.

This bit is set by user to enable I2C slave mode.

This bit is cleared by the user to disable I2C slave mode.

I2C Slave Status Registers, I2CxSSTA

Name:

I2C0SSTA, I2C1SSTA

Address:

0xFFFF082C, 0xFFFF092C

Default value:

0x0000, 0x0000

Access:

Read/write

Function:

These 16-bit MMRs are the I2C status registers in slave mode.

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