ADUC7023BCPZ62I-R7 datasheet(62/98 Pages) AD

62 / 98 page

ADuC7023

Data Sheet

Rev. H | Page 62 of 98

I2CxADR0[0] is the read/write bit.

In order to perform a read from a slave with a 10-bit address,

the master must first send a 10-bit address with the read/write

bit cleared. The master must then generate a repeated start and

send only the first byte of the address again, this time with the

read/write bit set. A repeated start is generated by writing to

I2CxADR0 while the master is still busy.

I2C REGISTERS

The I2C peripheral interfaces consist of a number of MMRs. These are described in the following section.

I2C Master Registers

I2C Master Control Registers, I2CxMCON

Name:

I2C0MCON, I2C1MCON

Address:

0xFFFF0800, 0xFFFF0900

Default value:

0x0000, 0x0000

Access:

Read/write

Function:

These 16-bit MMRs configure the I2C peripheral in master mode.

Table 65. I2CxMCON MMR Bit Designations

Bit

Name

Description

15 to 9

Reserved. These bits are reserved and should not be written to.

I2CMCENI

I2C transmission complete interrupt enable bit.

This bit is set to enable an interrupt on detecting a stop condition on the I2C bus.

This bit clears this interrupt source.

I2CNACKENI

I2C no acknowledge received interrupt enable bit.

This bit is set to enable interrupts when the I2C master receives a no acknowledge.

This bit clears this interrupt source.

I2CALENI

I2C arbitration lost interrupt enable bit.

This bit is set to enable interrupts when the I2C master has lost in trying to gain control of the I2C bus.

This bit clears this interrupt source.

I2CMTENI

I2C transmit interrupt enable bit.

This bit is set to enable interrupts when the I2C master has transmitted a byte.

This bit clears this interrupt source.

I2CMRENI

I2C receive interrupt enable bit.

This bit is set to enable interrupts when the I2C master receives data.

This bit is cleared by the user to disable interrupts when the I2C master is receiving data.

Reserved. Write a value of 0 to this bit.

I2CILEN

I2C internal loopback enable bit.

This bit is set to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to

their respective input signals.

This bit is cleared by the user to disable loopback mode.

I2CBD

I2C master backoff disable bit.

This bit is set to allow the device to compete for control of the bus even if another device is currently driving a

start condition.

This bit is cleared to back off until the I2C bus becomes free.

I2CMEN

I2C master enable bit.

This bit is set by the user to enable I2C master mode.

This bit is cleared to disable I2C master mode.

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