ADUC7023BCPZ62I-R7 datasheet(44/98 Pages) AD

44 / 98 page

ADuC7023

Data Sheet

Rev. H | Page 44 of 98

REMAP Register

Name:

REMAP

Address:

0xFFFF0220

Default value:

0x00

Access:

Read/write

Table 36. REMAP MMR Bit Designations

Bit

Name

Description

7 to 5

Reserved.

Read-only bit. Indicates the size of the

Flash/EE memory available. If this bit is set,

only 32 kB of Flash/EE memory is available.

Read-only bit. Indicates the size of the

SRAM memory available. If this bit is set,

only 4 kB of SRAM is available.

2 to 1

JTAFO

Read only bits. See the P0.0/BM description

for further details. The kernel sets these bits

to [11] if BM = 0 and 0x80014 ≠

0xFFFFFFFF at reset.

If these bits are set to [00], then P0.1/P0.2/

P0.3 are configured as JTAG pins. P0.1/P0.2

cannot be used as GPIO. P0.3 can be used

as GPIO, but this disables JTAG access.

If these bits are set to [1x], then P0.1/P0.2/

P0.3 are configured as GPIO pins. P0.1/P0.2/

P0.3 can also be used as JTAG, but JTAG

access is disabled if they are used as GPIO.

These bits are configured by the kernel

after any reset sequence and depend on

the state of P0.0 and the value at Address

0x80014 during the last reset sequence.

Remap

Remap bit.

This bit is set by the user to remap the

SRAM to Address 0x00000000.

This bit is cleared automatically after reset

to remap the Flash/EE memory to Address

0x00000000.

Reset Operation

There are four kinds of reset: external, power-on, watchdog

expiration, and software force. The RSTSTA register indicates

the source of the last reset, and RSTCLR allows clearing of the

RSTSTA register. These registers can be used during a reset

exception service routine to identify the source of the reset. If

RSTSTA is null, the reset is external.

The RSTCFG register allows different peripherals to retain their

state after a watchdog or software reset.

RSTSTA Register

Name:

RSTSTA

Address:

0xFFFF0230

Default value:

0x01

Access:

Read/write

Table 37. RSTSTA MMR Bit Designations

Bit

Description

7 to 3

Reserved.

Software reset.

This bit is set by the user to force a software reset.

This bit is cleared by setting the corresponding bit

in RSTCLR.

Watchdog timeout.

This bit is set automatically when a watchdog

timeout occurs.

This bit is cleared by setting the corresponding bit

in RSTCLR.

Power-on reset.

This bit is set automatically when a power-on reset

occurs.

This bit is cleared by setting the corresponding bit

in RSTCLR.

RSTCLR Register

Name:

RSTCLR

Address:

0xFFFF0234

Default value:

0x00

Access:

Write

Function:

Note that to clear the RSTSTA register, users

must write the Value 0x07 to the RSTCLR

RSTCFG Register

Name:

RSTCFG

Address:

0xFFFF024C

Default value:

0x00

Access:

Read/write

ADUC7023BCPZ62I-R7 bảng dữ liệu(PDF) 44 Page - Analog Devices

ADUC7023BCPZ62I-R7 bảng dữ liệu(HTML) 44 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

bảng dữ liệu tải về

Link URL