26HS01GTAM03 datasheet(163/166 Pages) INFINEON

163 / 166 page

Datasheet

163 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Revision history

Rev.

Submission

date

Description of change

2015-04-27

Initial release.

2015-06-12

Restructured datasheet.

Updated Features on page 1: Added SPI SDR (1-1-1).

Added Figure 1, Logic Block Diagram on page 4.

Updated Figure 4, Wear Leveling Sector Pool 4KB Parameter Sector Top or

Bottom on page 10.

Updated Table 4, Maximum Operating Frequency for Latency Code Options

on page 17.

Updated Table 19, Volatile Configuration Registers on page 40.

Table 23, VCR1 and NVCR1 Configuration Register Bit Assignments

on page 43: changed xVCR1[2] to Reserved.

Updated Table 29, SEC Register Bit Assignments on page 48.

Table 32, ECC Bit Assignments on page 56: removed EECC,

EECCD, ECCDI.

Updated Table 47, Command Definitions on page 72: Added Note.

Updated Table 64, Valid Combinations — Forecast on page 101.

Updated Copyright and Disclaimer.

2016-12-21

Removed MCPs.

Added Channel / Bus CRC.

Updated Sales Page and Disclaimer.

2017-03-27

Updated AC/DC Parameters

2017-06-13

Added SPI mode.

Updated INT# behavior based on SMC.

Updated DS behavior based on SMC.

Updated AC parameters based on the new Vih/Vil methodology (xSPI JEDEC).

Updated CYPRESS logo, Sales page, and Copyright information.

2017-08-22

Added (section 2.7).

Changed tCSHI to 6 ns (minimum).

Added Reset, ASO Exit, Status Register Read and Status register Clear commands are globally applicable in all

ASOs (section 18.1).

Added Data out during a Register Read transaction is only valid during the first word output by the device.

Subsequent data values output if CK/CK# continue to toggle while CS# remains Low are undefined (section 5.2).

Added Deep Power Down Upon POR is enabled, CS# must be maintained High during power-up.

Updated Exit from DPD waveform (section 21.7.1).

Added Wrap feature is not available in AutoBoot mode when Reading from the memory array (section 18.1).

Added Interface CRC register Read tCSHI to 20 ns (section 22.2.3).

2017-10-31

Updated Part Numbers.

Updated AC/DC parameters.

Updated Section “16. Device ID, Common Flash Interface and Serial Flash Discoverable Parameters (ID-SFDP) ASO

Map“.

Updated Test Specification table.

Updated Figure 35. Input/Output Waveforms and Measurement Levels.

2018-02-08

Changes per EROS Rev *G.

2018-04-06

Updated template.

2019-05-08

Preliminary datasheet

2018-07-10

Updated Timing parameters.

Updated SafeBoot.

Updated Interface CRC.

2018-09-24

Updated to Infineon template.

Clarification on 4KB Sector endurance cycles.

Removed Status and Configuration register protection password protection scheme.

Included Data Integrity Check Abort recovery flow.

Updated SafeBoot flow.

Included a clarification on Status Register and INT# value during resets.

Included example for 64-byte wrapped burst address sequence for 20 cycles latency.

Updated default latency to 16 cycles.

Included 1G Thermal resistance values.

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