26HS01GTAM03 datasheet(50/166 Pages) INFINEON

50 / 166 page

Datasheet

50 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.6.3

Configuration corruption detection (HYPERBUS™ interface)

If during device’s configuration update with HYPERBUS™ interface, such as erasing and writing to a Nonvolatile

interrupted. The device will return to Standby mode, but the Nonvolatile Register data is most likely corrupted

since the embedded erase or write operation was prematurely terminated.

SEMPER™ Flash with HYPERBUS™ interface will flag the PRGERR (STRV[4]) bit in case of a power loss occurs or a

hardware reset is initiated during erasing the Nonvolatile Configuration Register. Therefore, it is recommended

to poll the Status Register before writing the Nonvolatile Configuration registers. Upon detecting corruption in

the configuration, the device supports the read latency of 20 cycles.

Before initiating the normal operation, it is recommended to verify the device configuration after Nonvolatile

required to rewrite the configuration again in HYPERBUS™ interface.

4.6.4

Configuration corruption detection - (x1 Legacy SPI)

If during device’s configuration update with legacy SPI (1S-1S-1S) protocol, such as writing to a Nonvolatile

The device will return to Standby mode but the Nonvolatile Register data is most likely corrupted since the

embedded write operation was prematurely terminated. During the next power-up, the configuration corruption

is detected with appropriate failure flags displayed in the Status Register allowing rewriting the configuration

again. The device will maintain the configured protection scheme.

Table 36 shows the device’s Status Register bits upon detecting a configuration corruption.

Table 36

Status register 1 configuration corruption detection signature

Bit

Field name

Function

Detection signature

STR1V[7]

RESVRD

Reserved for Future Use

STR1V[6]

PRGERR

Programming Error Status Flag

STR1V[5]

ERSERR

Erasing Error Status Flag

STR1V[4]

RESVRD

Reserved for Future Use

STR1V[3]

STR1V[2]

STR1V[1]

WRPGEN

Write/Program Enable Status Flag

STR1V[0]

RDYBSY

Device Ready/Busy Status Flag

Table 37

Interface configuration upon detecting configuration corruption

Interface

Transactions supported

Address (# of bytes)

Frequency of operation

Output impedance

Legacy (x1) SPI

All SPI Transactions

Maximum

45 

Note

20. If you have Vcc within specifications and a hardware reset does not resolve the issue, replace the flash device.

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