26HS01GTAM03 datasheet(69/166 Pages) INFINEON

69 / 166 page

Datasheet

69 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.10.1.3

Program granularity

The S26HS-T/S26HL-T supports two methods of programming, Word or Write Buffer Programming.

Word programming examines the data word supplied by the command and programs 0’s in the addressed

memory array word to match the 0’s in the command data word.

Write Buffer Programming examines the write buffer and programs 0’s in the addressed memory array Line to

match the 0’s in the write buffer. The write buffer does not need to be completely filled with data. It is allowed to

program as little as a single bit, several bits, a single word, a few words, a half-page, multiple half-pages, or the

entire buffer as one programming operation. Use of the write buffer method reduces host system overhead in

writing program commands and reduces memory device internal overhead in programming operations to make

Write Buffer Programming more efficient and thus faster than programming individual words with the Word

Programming command.

Each half-page can be programmed by either method. Half-pages programmed by different methods may be

mixed within a Line. Pages programmed by different methods may be mixed within a Line for the Industrial

Temperature version (40°C to +85°C) only. For the Industrial Plus version (40°C to +105°C) and Automotive

AEC-Q100 Grade 1 (40°C to +125°C), Grade 2 (40°C to +105°C) and Grade 3 (40°C to +85°C) versions, the device

will only support one programming operation on each page between erase operations. Moreover, Single Word

Programming command is also not supported.

Word Programming and Write Buffer Programming, more than once within a half-page, is supported for legacy

software compatibility. However, using Word Programming or Write Buffer Programming more than once within

a half-page without an erase will disable the device’s ECC functionality for that half-page. For applications

requiring multiple programming operations within the same half-page, it is recommended to add system

software Error Detection and Correction, to enhance the data integrity of half-pages.

Note that if 2-bit ECC is enabled, multiple Word Programming or Write Buffer Programming within the same page

will result in a Program Error.

Future silicon process generations of HYPERFLASH™ may no longer support multiple program operations, within

the same half-page, without an erase operation on the sector containing the half-page. Planning for software

migration to future generations should adopt data structures and data management methods that can support

only one programming operation, per half-page, per erase.

4.10.1.4

Incremental programming

The same word location or half-page may be programmed more than once, by either the Word or Write Buffer

Programming methods, to incrementally change 1’s to 0’s. However as noted in Program granularity on page

69, incremental programming affects ECC syndrome bits and causes the device to disable ECC for that half-page.

Note that if 2-bit ECC is enabled, incremental Word Programming or Write Buffer Programming within the same

page will result in a Program Error.

4.10.1.5

Program register transactions

The Program Register (PRNPOR_4_0, PGVINC_4_0, PGVINS_4_0, PGVCR1_4_0, PGVCR2_4_0, PGNCR1_4_0,

PGNCR2_4_0, PGOASP_2_1, PGNPWD_2_1, PGNATB_2_1, PGOENX_2_1) transactions provide a way to program

any device register, Nonvolatile or Volatile. The transactions include unlock cycles followed by one word of data

to write.

4.10.1.6

Program SSR transaction

The Program Secure Silicon transaction (PG_SSR_4_1) programs data in the SSR, which is in a different address

space from the main array data and is OTP. The SSR is 1024 bytes, so the address bits from A31 to A10 must be

zero for this transaction.

The PRGERR bit in STRV[4] may be checked to determine if any error occurred during the operation.

4.10.1.7

Set dynamic protection bits (DYB)

The Set Dynamic Protect Bits (STVDYB_2_1) transaction sets a bit in the DYB Register to protect the addressed

sector from being programed or erased.

Notes

22. See Table 120 for the command sequence as required for Write Buffer Programming.

23. When the Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with

data, all addresses MUST fall within the selected Line.

26HS01GTAM03 bảng dữ liệu(PDF) 69 Page - Infineon Technologies AG

26HS01GTAM03 bảng dữ liệu(HTML) 69 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL