26HS01GTAM03 datasheet(76/166 Pages) INFINEON

76 / 166 page

Datasheet

76 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.11.10

HYPERBUS™ erase related registers and transaction

4.11.11

Legacy (x1) SPI erase related registers and transaction

4.12

Suspend and resume embedded operation

HL-T/HS-T device can interrupt and suspend the running embedded operations such as Erase, Program, or Data

Integrity Check. It can also resume the suspended operation once the host finishes the intermediate operation

and sends the respective resume transaction to the device.

4.12.1

Erase, program, or data integrity check suspend

The Suspend transaction allows the system to interrupt a program, erase or data integrity check operation and

then read from any other non erase-suspended sector, non-program-suspended-page or the array. The Device

Ready/Busy Status Flag (RDYBSY) in Status Register (SPI - STR1V[0], HYPERBUS™ STRV[7]) must be checked to

know when the program, erase or data integrity check operation has stopped.

4.12.1.1

Program suspend

• Program Suspend is valid only during a programming operation.

• The Program Operation Suspend Status flag (SPI - PROGMS STR2V[0], HYPERBUS™ - PROGMS STRV[2]) can be

usedtodetermineifaprogrammingoperationhasbeensuspendedorwascompletedatthetimeRDYSYchanges

to 0.

• A program operation can be suspended to allow a read operation.

• Reading at any address within a program-suspended page produces undetermined data.

Table 54

HYPERBUS™ erase related registers and transactions

Related registers

(see Section 5.2 HYPERBUS™ registers on page 90)

Related HYPERBUS™ transactions

(see Table 120 on page 124)

HYPERBUS™ Status Register (STRV)

Erase Sector (ERSCTR_6_0)

HYPERBUS™ Configuration Register 1 (CFR1N, CFR1V)

Erase Chip (ERCHIP_6_0)

SPI ASP PPB Lock (PPLV)

HYPERBUS™ ASP PPB Lock (PPLV)

Erase Nonvolatile Persistent Protection Bits (ERNPPB_2_1)

HYPERBUS™ Sector Erase Count Register (SECV)

Evaluate Erase Status (EVERST_1_0)

Sector Erase Count (RDSECV_1_0)

Table 55

Legacy (x1) SPI erase related registers and transactions

Related registers

(see Section 5.3 Legacy (x1) SPI registers on page 106)

Related SPI transactions

(see Table 122 on page 137)

SPI Status Register 1 (STR1N, STR1V)

Write Enable (WRENB_0_0)

SPI Status Register 2 (STR2V)

Erase 4KB Sector (ER004_4_0)

SPI ASP PPB Lock (PPLV)

Erase Chip (ERCHP_0_0)

SPI Sector Erase Count Register (SECV)

Sector Erase Count (SEERC_4_0)

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