26HS01GTAM03 datasheet(83/166 Pages) INFINEON

83 / 166 page

Datasheet

83 of 166

002-12337 Rev. *Y

2022-01-18

256Mb/512Mb/1Gb SEMPER™ Flash

HYPERBUS™ interface, 1.8V/3.0V

Features

4.15.2

Power-on reset (POR)

The device executes a POR process until a time delay of tPU has elapsed after the moment that VCC rises above

the minimum VCC threshold (see Figure 42 and Figure 43). The device must not be selected during power-up

(tPU). Therefore, CS# must rise with VCC. No commands may be sent to the device until the end of tPU. See

Table 129 for timing specifications.

RESET# is ignored during POR. If RESET# is LOW during POR and remains LOW through and beyond the end of

tPU, CS# must remain HIGH until tRS after RESET# returns HIGH.

Figure 42

Reset LOW at the end of POR

Figure 43

Reset HIGH at the end of POR

4.15.3

CS# signaling reset

The CS# Signaling Reset requires CS# and DQ0 signals. This reset method defines a signaling protocol, using

existing signals, to initiate an SPI flash hardware reset, independent of the device operating mode or number of

package pins.

The Signaling Protocol is shown in Figure 44. See Table 129 for timing specifications. The CS# signaling reset

steps are as follows:

• CS# is driven active LOW.

• CK remains stable in either HIGH or LOW state.

• CS# and DQ0 are both driven LOW.

• CS# is driven HIGH (inactive).

• Repeat the above four steps, each time alternating the state of DQ0 for a total of four times.

• Reset occurs after the fourth CS# cycle completes and it goes HIGH (inactive).

After the fourth CS# pulse, the slave triggers its internal reset, the device terminates any operation in progress,

makes all outputs high impedance, and ignores all read/write transactions for the duration of tRESET. Then the

device will be in standby state.

26HS01GTAM03 bảng dữ liệu(PDF) 83 Page - Infineon Technologies AG