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TMS320F28375DPZP bảng dữ liệu(HTML) 140 Page - Texas Instruments |
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140 / 226 page  8.11.5.1 SDFM Electrical Data and Timing (Using ASYNC) SDFM operation with asynchronous GPIO is defined by setting GPyQSELn = 0b11. Section 8.11.5.1.1 lists the SDFM timing requirements when using the asynchronous GPIO (ASYNC) option. Figure 8-56 through Figure 8-59 show the SDFM timing diagrams. 8.11.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option MIN MAX UNIT Mode 0 tc(SDC)M0 Cycle time, SDx_Cy 40 256 * SYSCLK period ns tw(SDCH)M0 Pulse duration, SDx_Cy high 10 tc(SDC)M0 – 10 ns tsu(SDDV-SDCH)M0 Setup time, SDx_Dy valid before SDx_Cy goes high 5 ns th(SDCH-SDD)M0 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns Mode 1 tc(SDC)M1 Cycle time, SDx_Cy 80 256 * SYSCLK period ns tw(SDCH)M1 Pulse duration, SDx_Cy high 10 tc(SDC)M1 – 10 ns tsu(SDDV-SDCL)M1 Setup time, SDx_Dy valid before SDx_Cy goes low 5 ns tsu(SDDV-SDCH)M1 Setup time, SDx_Dy valid before SDx_Cy goes high 5 ns th(SDCL-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes low 5 ns th(SDCH-SDD)M1 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns Mode 2 tc(SDD)M2 Cycle time, SDx_Dy 8 * tc(SYSCLK) 20 * tc(SYSCLK) ns tw(SDDH)M2 Pulse duration, SDx_Dy high 10 ns tw(SDD_LONG_KEEPOUT)M2 SDx_Dy long pulse duration keepout, where the long pulse must not fall within the MIN or MAX values listed. Long pulse is defined as the high or low pulse which is the full width of the Manchester bit-clock period. This requirement must be satisfied for any integer between 8 and 20. (N * tc(SYSCLK)) – 0.5 (N * tc(SYSCLK)) + 0.5 ns tw(SDD_SHORT)M2 SDx_Dy Short pulse duration for a high or low pulse (SDD_SHORT_H or SDD_SHORT_L). Short pulse is defined as the high or low pulse which is half the width of the Manchester bit-clock period. tw(SDD_LONG) / 2 – tc(SYSCLK) tw(SDD_LONG) / 2 + tc(SYSCLK) ns tw(SDD_LONG_DUTY)M2 SDx_Dy Long pulse variation (SDD_LONG_H – SDD_LONG_L) – tc(SYSCLK) tc(SYSCLK) ns tw(SDD_SHORT_DUTY)M2 SDx_Dy Short pulse variation (SDD_SHORT_H – SDD_SHORT_L) – tc(SYSCLK) tc(SYSCLK) ns Mode 3 tc(SDC)M3 Cycle time, SDx_Cy 40 256 * SYSCLK period ns tw(SDCH)M3 Pulse duration, SDx_Cy high 10 tc(SDC)M3 – 5 ns tsu(SDDV-SDCH)M3 Setup time, SDx_Dy valid before SDx_Cy goes high 5 ns th(SDCH-SDD)M3 Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 140 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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