TMS320F28375DPZP datasheet(78/226 Pages) TI

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8.9.7.1 External Interrupt (XINT) Electrical Data and Timing

Section 8.9.7.1.1 lists the external interrupt timing requirements. Section 8.9.7.1.2 lists the external interrupt

switching characteristics. Figure 8-16 shows the external interrupt timing.

8.9.7.1.1 External Interrupt Timing Requirements

MIN

MAX

UNIT(1)

tw(INT)

Pulse duration, INT input low/high

Synchronous

2tc(SYSCLK)

cycles

With qualifier

tw(IQSW) + tw(SP) + 1tc(SYSCLK)

cycles

(1)

For an explanation of the input qualifier parameters, see Section 8.9.6.2.1.

8.9.7.1.2 External Interrupt Switching Characteristics

over recommended operating conditions (unless otherwise noted)(1)

PARAMETER

MIN

MAX

UNIT

td(INT) Delay time, INT low/high to interrupt-vector fetch(2)

tw(IQSW) + 14tc(SYSCLK)

tw(IQSW) + tw(SP) + 14tc(SYSCLK)

cycles

(1)

For an explanation of the input qualifier parameters, see Section 8.9.6.2.1.

(2)

This assumes that the ISR is in a single-cycle memory.

Interrupt Vector

XINT1, XINT2, XINT3,

XINT4, XINT5

Address bus

(internal)

w(INT)

d(INT)

Figure 8-16. External Interrupt Timing

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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