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STM32H723VG bảng dữ liệu(PDF) 181 Page - STMicroelectronics

tên linh kiện STM32H723VG
Giải thích chi tiết về linh kiện  32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
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STM32H723VG bảng dữ liệu(HTML) 181 Page - STMicroelectronics

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DS13313 Rev 2
181/227
STM32H723xE/G
Electrical characteristics
208
6.3.31
Digital filter for Sigma-Delta Modulators (DFSDM) characteristics
Unless otherwise specified, the parameters given in Table 97 for DFSDM are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 12: General operating conditions.
•
Output speed is set to OSPEEDRy[1:0] = 10
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
VOS level set to VOS0
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (DìFSDM_CKINx, DFSDM_DATINx, DFSDM_CKOUT for DFSDM).
Table 97. DFSDM measured timing
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDFSDMCLK
DFSDM
clock
1.62 < VDD < 3.6 V
-
-
fSYSCLK
MHz
fCKIN
(1/TCKIN)
Input clock
frequency
SPI mode
(SITP[1:0] = 0,1),
External clock mode
(SPICKSEL[1:0] = 0)
--
20
SPI mode
(SITP[1:0] = 0,1),
Internal clock mode
(SPICKSEL[1:0] # 0)
--
20
fCKOUT
Output clock
frequency
1.62 < VDD < 3.6 V
-
-
20
DuCyCKOUT
Output clock
frequency
duty cycle
1.62 < VDD
< 3.6 V
Even
division,
CKOUTDIV
= n, 1, 3, 5..
45
50
55
%
Odd
division,
CKOUTDIV
= n, 2, 4, 6..
(((n/2+1)/(n+1))
*100)−5
(((n/2+1)/(n+1))
*100)
(((n/2+1)/(n+1))
*100)+5



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