STM32H723VG datasheet(28/227 Pages) STMICROELECTRONICS

tên linh kiện	STM32H723VG

Giải thích chi tiết về linh kiện	32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces

PDF	227 Pages

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Functional overview

STM32H723xE/G

28/227

DS13313 Rev 2

3.9.2

System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for

the debug, part of the RCC and power controller status registers, as well as the backup

power domain.

A system reset is generated in the following cases:

•

Power-on reset (pwr_por_rst)

•

Brownout reset

•

Low level on NRST pin (external reset)

•

Window watchdog

•

Independent watchdog

•

Software reset

•

Low-power mode security reset

•

Exit from Standby

3.10

General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs (except debug pins) are in Analog mode to reduce power

consumption (refer to GPIOs register reset values in the device reference manual).

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

3.11

Bus-interconnect matrix

The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow

the interconnection of bus masters with bus slaves (see Figure 3).

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