STM32H723VG datasheet(47/227 Pages) STMICROELECTRONICS

47 / 227 page

DS13313 Rev 2

47/227

STM32H723xE/G

Functional overview

The LPUART has a clock domain independent from the CPU clock, and can wakeup the

system from Stop mode. The wakeup from Stop mode are programmable and can be done

on:

•

Start bit detection

•

Any received data frame

•

A specific programmed data frame

•

Specific TXFIFO/RXFIFO status when FIFO mode is enabled.

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to

9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame

while having an extremely low energy consumption. Higher speed clock can be used to

reach higher baudrates.

LPUART interface can be served by the DMA controller.

3.36

Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)

The devices feature up to six SPIs (SPI2S1, SPI2S2, SPI2S3, SPI4, SPI5 and SPI2S6) that

allow communicating up to 150 Mbits/s in Master and Slave modes, in Half-duplex, Full-

duplex and Simplex modes. The 3-bit prescaler gives 8 master mode frequencies and the

frame is configurable from 4 to 16 bits. All SPI interfaces support NSS pulse mode, TI mode,

Hardware CRC calculation and 8x 8-bit embedded Rx and Tx FIFOs with DMA capability.

Four standard I2S interfaces (multiplexed with SPI1, SPI2, SPI3 and SPI6) are available.

They can be operated in Master or Slave mode, in Simplex communication modes, and can

be configured to operate as a 16-/32-bit resolution input or output channel (except SPI2S6

which is limited to 16 bits). Audio sampling frequencies from 8 kHz up to 192 kHz are

supported. When either or both of the I2S interfaces is/are configured in Master mode, the

master clock can be output to the external DAC/CODEC at 256 times the sampling

frequency. All I2S interfaces support 16x 8-bit embedded Rx and Tx FIFOs with DMA

capability.

3.37

Serial audio interfaces (SAI)

The devices embed 2 SAIs (SAI1, and SAI4) that allow designing many stereo or mono

audio protocols such as I2S, LSB or MSB-justified, PCM/DSP, TDM or AC’97. An SPDIF

output is available when the audio block is configured as a transmitter. To bring this level of

flexibility and reconfigurability, the SAI contains two independent audio sub-blocks. Each

block has it own clock generator and I/O line controller.

Audio sampling frequencies up to 192 kHz are supported.

In addition, up to 8 microphones can be supported thanks to an embedded PDM interface.

The SAI can work in master or slave configuration. The audio sub-blocks can be either

receiver or transmitter and can work synchronously or asynchronously (with respect to the

other one). The SAI can be connected with other SAIs to work synchronously.

STM32H723VG bảng dữ liệu(PDF) 47 Page - STMicroelectronics

STM32H723VG bảng dữ liệu(HTML) 47 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL