STM32H723VG datasheet(14/227 Pages) STMICROELECTRONICS

14 / 227 page

Description

STM32H723xE/G

14/227

DS13313 Rev 2

Description

STM32H723xE/G devices are based on the high-performance Arm® Cortex®-M7 32-bit

RISC core operating at up to 550 MHz. The Cortex® -M7 core features a floating point unit

(FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision

data-processing instructions and data types. The Cortex -M7 core includes 32 Kbytes of

instruction cache and 32 Kbytes of data cache. STM32H723xE/G devices support a full set

of DSP instructions and a memory protection unit (MPU) to enhance application security.

STM32H723xE/G devices incorporate high-speed embedded memories with up to 1 Mbyte

of Flash memory, up to 564 Kbytes of RAM (including 192 Kbytes that can be shared

between ITCM and AXI, plus 64 Kbytes exclusively ITCM, plus 128 Kbytes exclusively AXI,

128 Kbyte DTCM, 48 Kbytes AHB and 4 Kbytes of backup RAM), as well as an extensive

range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit

multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external

memory access. To improve application robustness, all memories feature error code

correction (one error correction, two error detections).

The devices embed peripherals allowing mathematical/arithmetic function acceleration

(CORDIC co-processor for trigonometric functions and FMAC unit for filter functions). All the

devices offer three ADCs, two DACs, two operational amplifiers, two ultra-low power

comparators, a low-power RTC, 4 general-purpose 32-bit timers, 12 general-purpose 16-bit

timers including two PWM timers for motor control, five low-power timers, a true random

number generator (RNG). The devices support four digital filters for external sigma-delta

modulators (DFSDM). They also feature standard and advanced communication interfaces.

•

Standard peripherals

–Five I2Cs

–

Five USARTs, five UARTs and one LPUART

–

Six SPIs, four I2Ss in Half-duplex mode. To achieve audio class accuracy, the I2S

peripherals can be clocked by a dedicated internal audio PLL or by an external

clock to allow synchronization. (Note that the five USARTs also provide SPI slave

capability.)

–

Two SAI serial audio interfaces

–

One SPDIFRX interface with four inputs

–

One SWPMI (Single Wire Protocol Master Interface)

–

Management Data Input/Output (MDIO) slaves

–

Two SDMMC interfaces

–

A USB OTG high-speed interface with full-speed capability (with the ULPI)

–

Two FDCANs plus one TT-FDCAN interface

–

An Ethernet interface

–

Chrom-ART Accelerator

–

HDMI-CEC

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