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VR4102 bảng dữ liệu(PDF) 152 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
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VR4102 bảng dữ liệu(HTML) 152 Page - NEC

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CHAPTER 5 MEMORY MANAGEMENT SYSTEM
152
5.5.8 Cache Tag Registers (TagLo (28) and TagHi (29))
The TagLo and TagHi registers are 32-bit read/write registers that hold the primary cache tag and parity during
cache initialization, cache diagnostics, or cache error processing. The Tag registers are written by the CACHE and
MTC0 instructions.
The P fields of these registers are ignored on Index Store Tag operations by the CACHE instruction. Parity is
computed by the store operation. Figure 5-19 shows the format of these registers.
Figure 5-19. TagLo and TagHi Registers
22
0
31
10
9
8
7
1
2
6
PTagLo
V
D
W
0
W
’ P
1
1
1
1
1
5
22
0
31
10
9
8
1
PTagLo
V
0
P
1
1
8
0
31
0
32
Instruction
cache
Data cache
Tag Hi
PTagLo: Specifies physical address bits 31 to 10.
V
: Valid bit
D
: Dirty bit. However, this bit is defined only for the compatibility with the VR4000 Series processors,
and does not indicate the status of cache memory in spite of its readability and writability. This bit
cannot change the status of cache memory.
W
: Write-back bit (set if cache line has been updated)
W’
: Even parity for the write-back bit
P
: Even parity bit for primary cache tag
0
: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.



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