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VR4102 bảng dữ liệu(PDF) 134 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
Trang chủ  http://www.nec.com/
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VR4102 bảng dữ liệu(HTML) 134 Page - NEC

Back Button VR4102 Datasheet HTML 130Page - NEC VR4102 Datasheet HTML 131Page - NEC VR4102 Datasheet HTML 132Page - NEC VR4102 Datasheet HTML 133Page - NEC VR4102 Datasheet HTML 134Page - NEC VR4102 Datasheet HTML 135Page - NEC VR4102 Datasheet HTML 136Page - NEC VR4102 Datasheet HTML 137Page - NEC VR4102 Datasheet HTML 138Page - NEC Next Button
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CHAPTER 5 MEMORY MANAGEMENT SYSTEM
134
(10) 64-bit Kernel mode compatible spaces (ckseg0, ckseg1, cksseg, and ckseg3)
If the conditions listed below are satisfied in Kernel mode, ckseg0, ckseg1, cksseg, or ckseg3 (each having 512
Mbytes) is selected as a compatible space according to the state of the bits 30 and 29 (two low-order bits) of the
address.
— The KX bit of the Status register is 1.
— Bits 63 and 62 of the 64-bit virtual address are 11.
— Bits 61 to 31 of the virtual address are all 1.
(i)
ckseg0
This space is an unmapped region, compatible with the 32-bit mode kseg0 space. The K0 field of the Config
register controls cacheability and coherency.
(ii) ckseg1
This space is an unmapped and uncached region, compatible with the 32-bit mode kseg1 space.
(iii) cksseg
This space is the current supervisor virtual space, compatible with the 32-bit mode ksseg space.
References to cksseg are mapped through TLB. Whether cache can be used or not is determined by bit C of
each page’s TLB entry.
(iv) ckseg3
This space is the current supervisor virtual space, compatible with the 32-bit mode kseg3 space.
References to ckseg3 are mapped through TLB. Whether cache can be used or not is determined by bit C of
each page’s TLB entry.



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