VR4102 datasheet(125/701 Pages) NEC

125 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

125

Figure 5-5. Supervisor Mode Address Space

64-bit mode

32-bit mode

Note

0xDFFF FFFF

0xE000 0000

0xC000 0000

0xFFFF FFFF

Address error

0x0000 0010 0000

0000

0xFFFF FFFF FFFF FFFF

suseg

sseg

0x7FFF FFFF

0x0000 0000

0x8000 0000

xsuseg

xsseg

csseg

0xBFFF FFFF

0x4000 00FF FFFF FFFF

0x4000 0100 0000 0000

0x0000 000F FFFF

FFFF

0.5 Gbytes with

TLB mapping

Address error

2 Gbytes with

TLB mapping

Address error

0.5 Gbytes with

TLB mapping

Address error

1 Tbyte with

TLB mapping

Address error

1 Tbyte with

TLB mapping

0xFFFF FFFF E000 0000

0xFFFF FFFF DFFF FFFF

0xFFFF FFFF C000 0000

0xFFFF FFFF BFFF FFFF

0x3FFF FFFF FFFF FFFF

0x4000 0000 0000 0000

0x0000 0000 0000 0000

0x0000 00FF FFFF FFFF

0x0000 0100 0000 0000

Note

The VR4102 uses 64-bit addresses within it. For 32-bit mode addressing, bit 31 is sign-extended to bits

32 to 63, and the resulting 32 bits are used for addressing. Usually, it is impossible for 32-bit mode

programs to generate invalid addresses.

In an operation of base register + offset for addressing,

however, a two’s complement overflow may occur, causing an invalid address.

Note that the result

becomes undefined. Two factors that can cause a two’s complement follow:

— When offset bit 15 is 0, base register bit 31 is 0, and bit 31 of the operation “base register + offset” is 1

— When offset bit 15 is 1, base register bit 31 is 1, and bit 31 of the operation “base register + offset” is 0

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