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VR4102 bảng dữ liệu(PDF) 213 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
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VR4102 bảng dữ liệu(HTML) 213 Page - NEC

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CHAPTER 8 CACHE MEMORY
This chapter describes in detail the cache memory: its place in the VR4100 CPU core memory organization, and
individual organization of the caches.
This chapter uses the following terminology:
— The data cache may also be referred to as the D-cache.
— The instruction cache may also be referred to as the I-cache.
These terms are used interchangeably throughout this book.
8.1 MEMORY ORGANIZATION
Figure 8-1 shows the VR4100 CPU core system memory hierarchy. In the logical memory hierarchy, the caches
lie between the CPU and main memory. They are designed to make the speedup of memory accesses transparent
to the user.
Each functional block in Figure 8-1 has the capacity to hold more data than the block above it. For instance,
physical main memory has a larger capacity than the caches. At the same time, each functional block takes longer
to access than any block above it. For instance, it takes longer to access data in main memory than in the CPU on-
chip registers.
Figure 8-1. Logical Hierarchy of Memory
VR4100 CPU core
Register
Register
I-cache
D-cache
Cache
Main memory
Disc, CD-ROM,
tape, etc.
Register
Cache
Memory
Memory
media
Faster
access time
Increasing
data capacity



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