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VR4102 bảng dữ liệu(PDF) 202 Page - NEC

tên linh kiện VR4102
Giải thích chi tiết về linh kiện  64/32-bit Microprocessor
PDF  701 Pages
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nhà sản xuất  NEC [NEC]
Trang chủ  http://www.nec.com/
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VR4102 bảng dữ liệu(HTML) 202 Page - NEC

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CHAPTER 7 INITIALIZATION INTERFACE
202
7.1.3 Deadman’s Switch
After the Deadman’s switch unit is enabled, if the Deadman’s switch is not cleared within the specified time
period, the VR4102 is immediately returned to reset status.
Setting and clearing of the Deadman’s switch is
performed by software.
A reset by the Deadman’s switch initializes the entire internal state except for the RTC timer and the PMU. Since
the DRAM is not switched to self refresh mode, the contents of DRAM after a Deadman’s switch reset are not at all
guaranteed.
After a reset, the processor becomes the system bus master and it begins the Cold reset exception sequence to
access the reset vectors in the ROM space. Since only part of the internal status is reset when a reset occurs in the
VR4102, the processor should be completely initialized by software.
Figure 7-3. Deadman’s Switch
L
H
H
Reset#(internal)
ColdReset#(internal)
MPOWER(o)
POWER(i)
RSTSW#(i)
RTC
(internal, 32kHz)
16MasterClock
Note
16ms
PLL(internal)
Undefined
Stable oscillation
Stable oscillation
Stable oscillation
Note MasterClock is the basic clock used in the CPU core.



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