VR4102 datasheet(192/701 Pages) NEC

192 / 701 page

CHAPTER 6 EXCEPTION PROCESSING

192

Figure 6-14. Common Exception Handler (1/2)

(a) Processing exceptions other than Cold reset, Soft reset, NMI,

TLB/XTLB Mismatch, and Cache Error exceptions (hardware)

Instruction

in branch delay

slot?

BD bit

← 0

EPC

← PC

EXL

← 1

BEV

EntryHi

← VPN2, ASID

X/Context

← VPN2

Set Cause Register (ExcCode, CE)

BD bit

← 1

EPC

← PC – 4

Yes

; Kernel mode is set, and interrupts

are disabled.

← 0xFFFF FFFF BFC0 0200 + 180

(Unmapped, uncached space)

← 0xFFFF FFFF 8000 0000 + 180

(Unmapped, cacheable space)

To guideline of general exception handler

= 0 (normal)

= 1 (bootstrap)

EXL = 1?

(SR1)

Yes

Start

; Check for multiple exceptions

; BadVAddr is set only when a TLB

Mismatch, TLB Invalid, or TLB Modified

exception occurs. (BadVAddr is not set

when a Bus Error exception occurs.

; The EntryHi and X/Context registers are set

only when a TLB Mismatch, TLB Invalid, or

TLB Modified exception occurs.

Remark The exceptions can be masked by the IE or IM bit. The Watch exception can be set to pending status by

setting the EXL bit.

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