pertaining to the board construction that can affect performance. The following set of guidelines were developed

experimentally through several designs involving M-LVDS devices:

• Copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz

• All exposed circuitry should be solder-plated (60/40) to 7.62 μm or 0.0003 in (minimum).

• Copper plating should be 25.4 μm or 0.001 in (minimum) in plated-through-holes.

• Solder mask over bare copper with solder hot-air leveling

10.1.3 Recommended Stack Layout

Following the choice of dielectrics and design specifications, you must decide how many levels to use in the

stack. To reduce the TTL/CMOS to M-LVDS crosstalk, it is a good practice to have at least two separate signal

planes as shown in Figure 10-3.

Layer 4: Routed Plane (TTL/CMOS Signals)

Layer 3: Power Plane

Layer 2: Ground Plane

Layer 1: Routed Plane (MLVDS Signals)

Figure 10-3. Four-Layer PCB Board

Note

The separation between layers 2 and 3 should be 127 μm (0.005 in). By keeping the power and

ground planes tightly coupled, the increased capacitance acts as a bypass for transients.

One of the most common stack configurations is the six-layer board, as shown in Figure 10-4.

Layer 4: Routed Plane (TTL Signals)

Layer 3: Power Plane

Layer 2: Ground Plane

Layer 1: Routed Plane (MLVDS Signals)

Layer 4: Ground Plane

Layer 5: Ground Plane

Figure 10-4. Six-Layer PCB Board

In this particular configuration, it is possible to isolate each signal layer from the power plane by at least one

ground plane. The result is improved signal integrity; however, fabrication is more expensive. Using the 6-layer

board is preferable, because it offers the layout designer more flexibility in varying the distance between signal

layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6.

10.1.4 Separation Between Traces

The separation between traces depends on several factors; however, the amount of coupling that can be

tolerated usually dictates the actual separation. Low noise coupling requires close coupling between the

differential pair of an M-LVDS link to benefit from the electromagnetic field cancellation. The traces should be

100-Ω differential and thus coupled in the manner that best fits this requirement. In addition, differential pairs

should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew

and signal reflection.

In the case of two adjacent single-ended traces, one should use the 3-W rule, which stipulates that the distance

between two traces must be greater than two times the width of a single trace, or three times its width measured

from trace center to trace center. This increased separation effectively reduces the potential for crosstalk. The

same rule should be applied to the separation between adjacent M-LVDS differential pairs, whether the traces

are edge-coupled or broad-side-coupled.

SN65MLVD203B

SLLSFG7 – AUGUST 2020

www.ti.com

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