8.2.3.3 Driver Input Voltage

The input stage accepts LVTTL signals. The driver operates with a decision threshold of approximately 1.4 V.

8.2.3.4 Driver Output Voltage

The driver outputs a steady state common mode voltage of 1 V with a differential signal of 540 mV under

nominal conditions.

8.2.3.5 Termination Resistors

As shown earlier, an M-LVDS communication channel employs a current source driving a transmission line

which is terminated with two resistive loads. These loads serve to convert the transmitted current into a voltage

at the receiver input. To ensure good signal integrity, the termination resistors should be matched to the

characteristic impedance of the transmission line. The designer should ensure that the termination resistors are

within 10% of the nominal media characteristic impedance. If the transmission line is targeted for 100-Ω

impedance, the termination resistors should be between 90 Ω and 110 Ω. The line termination resistors are

typically placed at the ends of the transmission line.

8.2.3.6 Receiver Input Signal

The M-LVDS receivers herein comply with the M-LVDS standard and correctly determine the bus state. These

devices have Type-1 and Type-2 receivers that detect the bus state with as little as 50 mV of differential voltage

over the common mode range of –1 V to 3.4 V.

8.2.3.7 Receiver Input Threshold (Failsafe)

The MLVDS standard defines a Type-1 and Type-2 receiver. Type-1 receivers have their differential input voltage

thresholds near zero volts. Type-2 receivers have their differential input voltage thresholds offset from 0 V to

detect the absence of a voltage difference. The impact to receiver output by the offset input can be seen in Table

8-2 and Figure 8-3.

Table 8-2. Receiver Input Voltage Threshold Requirements

RECEIVER TYPE

OUTPUT LOW

OUTPUT HIGH

Type 1

Type 2

-100

-50

0

50

100

150

200

Type 1

Transition Regions

Type 2

Low

High

Low

High

Figure 8-3. Expanded Graph of Receiver Differential Input Voltage Showing Transition Region

8.2.3.8 Receiver Output Signal

Receiver outputs comply with LVTTL output voltage standards when the supply voltage is within the range of 3 V

to 3.6 V.

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SN65MLVD203B

SLLSFG7 – AUGUST 2020

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