Table 8-1. Design Parameters (continued)

PARAMETERS

VALUES

Interconnect characteristic impedance

100 Ω

Termination resistance (differential)

100 Ω

Number of receiver nodes

2 to 32

Receiver supply voltage

3 to 3.6 V

Receiver input voltage

Receiver signaling rate

DC to 200 Mbps

Ground shift between driver and receiver

±1 V

8.2.3 Detailed Design Procedure

8.2.3.1 Supply Voltage

The SN65MLVD203B is operated from a single supply. The device can support operations with a supply as low

as 3 V and as high as 3.6 V.

8.2.3.2 Supply Bypass Capacitance

Bypass capacitors play a key role in power distribution circuitry. At low frequencies, power supply offers very

low-impedance paths between its terminals. However, as higher frequency currents propagate through power

traces, the source is often incapable of maintaining a low-impedance path to ground. Bypass capacitors are

used to address this shortcoming. Usually, large bypass capacitors (10 μF to 1000 μF) at the board level do a

good job up into the kHz range. Due to their size and length of their leads, large capacitors tend to have large

inductance values at the switching frequencies. To solve this problem, smaller capacitors (in the nF to μF range)

must be installed locally next to the integrated circuit.

Multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass

capacitors in high-speed environments, because their lead inductance is about 1 nH. For comparison purposes,

a typical capacitor with leads has a lead inductance around 5 nH.

The value of the bypass capacitors used locally with M-LVDS chips can be determined by Equation 1 and

Equation 2, according to High Speed Digital Design – A Handbook of Black Magic by Howard Johnson and

Martin Graham (1993). A conservative rise time of 4 ns and a worst-case change in supply current of 100 mA

covers the whole range of M-LVDS devices offered by Texas Instruments. In this example, the maximum power

supply noise tolerated is 100 mV; however, this figure varies depending on the noise budget available for the

design.

Maximum Step Change Supply Current

chip

Rise Time

Maximum Power Supply Noise

I

C

T

V

æ

ö

D

=

´

ç

÷

ç

÷

D

è

ø

(1)

MLVDS

100 mA

C

4 ns

0.004

F

100 mV

æ

ö

=

´

=

m

ç

÷

è

ø

(2)

Figure 8-2 shows a configuration that lowers lead inductance and covers intermediate frequencies between the

board-level capacitor (>10 µF) and the value of capacitance found above (0.004 µF). Place the smallest value of

capacitance as close as possible to the chip.

0.1 µF

0.004 µF

3.3 V

Figure 8-2. Recommended M-LVDS Bypass Capacitor Layout

SN65MLVD203B

SLLSFG7 – AUGUST 2020

www.ti.com

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