ATTINY817-MFR. datasheet(112/492 Pages) MICROCHIP

112 / 492 page

Changes of the signal on a pin can trigger an interrupt. The exact conditions are defined by writing to the

Input/Sense bit field (ISC) in PORT.PINnCTRL.

When setting or changing interrupt settings, take these points into account:

•

If an INVEN bit is toggled in the same cycle as the interrupt setting, the edge caused by the

inversion toggling may not cause an interrupt request.

•

If an input is disabled while synchronizing an interrupt, that interrupt may be requested on re-

enabling the input, even if it is re-enabled with a different interrupt setting.

•

If the interrupt setting is changed while synchronizing an interrupt, that interrupt may not be

accepted.

•

Only few pins support full asynchronous interrupt detection, see I/O Multiplexing and

Considerations. These limitations apply for waking the system from sleep:

Interrupt Type

Fully Asynchronous Pins

Other Pins

BOTHEDGES

will wake system

RISING

will wake system

will not wake system

FALLING

will wake system

will not wake system

LEVEL

will wake system

Related Links

I/O Multiplexing and Considerations

16.3.3

Interrupts

Table 16-3. Available Interrupt Vectors and Sources

Offset Name

Vector Description

Conditions

0x00

PORTx PORT A, B, C interrupt INTn in PORT.INTFLAGS is raised as configured by ISC bit in

PORT.PINnCTRL.

Each PORT pin n can be configured as an interrupt source. Each interrupt can be individually enabled or

disabled by writing to ISC in PORT.PINCTRL.

When an interrupt condition occurs, the corresponding Interrupt Flag is set in the Interrupt Flags register

of the peripheral (peripheral.INTFLAGS).

An interrupt request is generated when the corresponding interrupt is enabled and the Interrupt Flag is

set. The interrupt request remains active until the Interrupt Flag is cleared. See the peripheral's

INTFLAGS register for details on how to clear Interrupt Flags.

Asynchronous Sensing Pin Properties

Table 16-4. Behavior Comparison of Fully/Partly Asynchronous Sense Pin

Property

Synchronous or Partly Asynchronous Sense

Support

Full Asynchronous Sense

Support

Minimum pulse width

to trigger interrupt

Minimum one system clock cycle

Less than a system clock

cycle

Waking the device

from sleep

From all interrupt sense configurations from sleep

modes with Main Clock running. Only from

BOTHEDGES or LEVEL interrupt sense

From all interrupt sense

configurations from all sleep

modes

ATtiny417/817

Datasheet Complete

DS40001901B-page 112

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