ATTINY817-MFR. datasheet(52/492 Pages) MICROCHIP

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General Operating Ratings

BOD - Brownout Detector

9.3.4

Interrupts

Table 9-3. Available Interrupt Vectors and Sources

Offset Name

Vector Description

Conditions

0x00

EEREADY NVM

The EEPROM is ready for new write/erase operations.

When an interrupt condition occurs, the corresponding Interrupt Flag is set in the Interrupt Flags register

of the peripheral (NVMCTRL.INTFLAGS).

An interrupt source is enabled or disabled by writing to the corresponding bit in the peripheral's Interrupt

Enable register (NVMCTRL.INTEN).

An interrupt request is generated when the corresponding interrupt source is enabled and the Interrupt

Flag is set. The interrupt request remains active until the Interrupt Flag is cleared. See the peripheral's

INTFLAGS register for details on how to clear Interrupt Flags.

9.3.5

Sleep Mode Operation

If there is no ongoing write operation, the NVMCTRL will enter sleep mode when the system enters sleep

mode.

If a write operation is ongoing when the system enters a sleep mode, the NVM block, the NVM Controller

and the system clock will remain on until the write is finished. This is valid for all sleep modes, including

Power Down sleep mode.

The EEPROM Ready interrupt will wake up the device only from Idle sleep mode.

The page buffer is cleared when waking up from sleep.

9.3.6

Configuration Change Protection

This peripheral has registers that are under Configuration Change Protection (CCP). In order to write to

these, a certain key must be written to the CPU.CCP register first, followed by a write access to the

protected bits within four CPU instructions.

It is possible to try writing to these registers any time, but the values are not altered.

The following registers are under CCP:

Table 9-4. NVMCTRL - Registers under Configuration Change Protection

Key

NVMCTRL.CTRLA

SPM

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