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ATTINY817-MFR. bảng dữ liệu(PDF) 95 Page - Microchip Technology

tên linh kiện ATTINY817-MFR.
Giải thích chi tiết về linh kiện  AVR짰 Microcontroller with Core Independent Peripherals and picoPower짰 Technology
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nhà sản xuất  MICROCHIP [Microchip Technology]
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ATTINY817-MFR. bảng dữ liệu(HTML) 95 Page - Microchip Technology

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SYNCCH0, SYNCCH1
ASYNCCH0, ASYNCCH1, ASYNCCH2, ASYNCCH3
SYNCUSER0, SYNCUSER1
ASYNCUSER0, ASYNCUSER1, ASYNCUSER2, ASYNCUSER3, ASYNCUSER4, ASYNCUSER5,
ASYNCUSER6, ASYNCUSER7, ASYNCUSER8, ASYNCUSER9, ASYNCUSER10
14.2.2
Signal Description
Internal Event Signaling
The Event signaling can either happen synchronously to the main clock (CLK_MAIN), or asynchronously
to it.
Depending on the underlying event, the Event signal can be a pulse with a duration of 1 clock cycle, or a
level signal (similar to a status flag).
Event Output to Pin
Signal
Type
Description
EVOUT[2:0]
Digital output
Event output
Related Links
I/O Lines
Block Diagram - CLKCTRL
14.2.3
System Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
Table 14-1. EVSYS System Dependencies
Dependency
Applicable
Peripheral
Clocks
Yes
CLKCTRL
I/O Lines and Connections
Yes
PORTMUX
Interrupts
No
-
Events
Yes
EVSYS
Debug
Yes
UPDI
Related Links
Clocks
Debug Operation
14.2.3.1 Clocks
The EVSYS uses the peripheral clock for I/O registers and software events. When set up correctly, the
routing network can be used also in sleep modes without any clock. Software Events will not work in
sleep modes where the peripheral clock is halted.
Related Links
CLKCTRL - Clock Controller
ATtiny417/817
© 2017 Microchip Technology Inc.
Datasheet Complete
DS40001901B-page 95



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