ATTINY817-MFR. datasheet(44/492 Pages) MICROCHIP

44 / 492 page

Only the number of bits required to address the available data memory including external memory (up to

64KB) is implemented for each device. Unused bits will always read as zero.

The CPU.SPL and CPU.SPH register pair represents the 16-bit value, CPU.SP. The low byte [7:0] (suffix

L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For

more details on reading and writing 16-bit registers, refer to Accessing 16-bit Registers.

To prevent corruption when updating the Stack Pointer from software, a write to CPU.SPL will

automatically disable interrupts for the next four instructions or until the next I/O memory write.

Name:

Offset: 0x0D

Reset:

0xxxxx

Property:

Bit

SP[15:8]

Access

R/W

Reset

Bit

SP[7:0]

Access

R/W

Reset

Bits 15:8 – SP[15:8]: Stack Pointer high byte

These bits hold the MSB of the 16-bit register.

Bits 7:0 – SP[7:0]: Stack Pointer low byte

These bits hold the LSB of the 16-bit register.

8.7.3

Status Register

The Status register contains information about the result of the most recently executed arithmetic or logic

instruction. For details about the bits in this register and how they are affected by the different

instructions, see the Instruction Set Summary.

Name:

SREG

Offset: 0x0F

Reset:

0x00

Property:

Bit

Access

R/W

Reset

Bit 7 – I: Global Interrupt Enable

Writing a '1' to this bit enable interrupts on the device.

ATtiny417/817

Datasheet Complete

DS40001901B-page 44

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