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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ATTINY817-MFR. bảng dữ liệu(PDF) 47 Page - Microchip Technology |
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ATTINY817-MFR. bảng dữ liệu(HTML) 47 Page - Microchip Technology |
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47 / 492 page  Table 9-1. NVMCTRL System Dependencies Dependency Applicable Peripheral Clocks Yes CLKCTRL I/O Lines and Connections No - Interrupts Yes CPUINT Events No - Debug Yes UPDI Related Links Clocks Debug Operation Interrupts 9.2.2.1 Clocks This peripheral always runs on the CPU clock (CLK_CPU). It will request this clock also in sleep modes if a write/erase is ongoing. Related Links CLKCTRL - Clock Controller 9.2.2.2 I/O Lines and Connections Not applicable. 9.2.2.3 Interrupts Using the interrupts of this peripheral requires the Interrupt Controller to be configured first. 9.2.2.4 Events Not applicable. 9.2.2.5 Debug Operation When run-time debugging, this peripheral will continue normal operation. Halting the CPU in debugging mode will halt normal operation of the peripheral. If the peripheral is configured to require periodical service by the CPU through interrupts or similar, improper operation or data loss may result during halted debugging. Related Links UPDI - Unified Program and Debug Interface 9.3 Functional Description 9.3.1 Memory Organization 9.3.1.1 Flash The Flash is divided into a set of pages. A page is the basic unit addressed when programming the Flash. It is only possible to write or erase a whole page at a time. One page consists of several words. The Flash can be divided into three sections in blocks of 256 bytes for different security. The three different sections are BOOT, application code (APPCODE) and application data (APPDATA). ATtiny417/817 © 2017 Microchip Technology Inc. Datasheet Complete DS40001901B-page 47 |
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