ATTINY817-MFR. datasheet(179/492 Pages) MICROCHIP

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21.2.1

Block Diagram

Figure 21-1. Timer/Counter Type B Block Diagram

Counter

CNT

= 0

"count"

"clear"

Control

EVCTRL

CTRLA

(INT Req.)

TOP

ClockSelect

BOTTOM

Edge Select

CTRLB

Mode

CCMP

Output control

and

logic

Asynchronous

Synchronous

output

Asynchronous

output

Mode, Output enable, initial value

CLK_PER

Logic

Event System

TCB

DIV2

CLK_TCA

21.2.1.1 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filter scheme. When the noise filter

is enabled the peripheral monitors the event channel and keeps a record of the last four observed

samples. If four consecutive samples are equal, the input is considered to be stable and the signal is fed

to the edge detector.

When enabled, the noise canceler introduces an additional delay of four system clock cycles between a

change applied to the input and the update of the input compare register.

The noise canceler uses the system clock and is therefore not affected by the prescaler.

21.2.2

Signal Description

Signal

Description

Type

Digital asynchronous output

Waveform Output

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