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56F8167 bảng dữ liệu(PDF) 18 Page - Freescale Semiconductor, Inc

tên linh kiện 56F8167
Giải thích chi tiết về linh kiện  16-bit Digital Signal Controllers
PDF  184 Pages
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56F8167 bảng dữ liệu(HTML) 18 Page - Freescale Semiconductor, Inc

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56F8367 Technical Data, Rev. 7.0
18
Freescale Semiconductor
Preliminary
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Note: Signals in italics are NOT available in the 56F8167 device.
Note: The 160 Map Ball Grid Array is not available in the 56F8167 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin
shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the
pin, it will become an input if no other registers are changed.
Note: LQFP Pin numbers and MBGA Ball numbers do not always correlate in Table 2-2. Please contact
factory for exact correlation.
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
Pin
No.
Ball No.
Type
State
During
Reset
Signal Description
VDD_IO
1
F4
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O
interface and also the Processor core through the on-chip voltage
regulator, if it is enabled.
VDD_IO
16
K5
VDD_IO
31
E5
VDD_IO
42
K7
VDD_IO
77
E9
VDD_IO
96
K10
VDD_IO
134
F11
VDDA_ADC
114
C14
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules.
It must be connected to a clean analog power supply.
VDDA_OSC_
PLL
92
K13
Supply
Oscillator and PLL Power — This pin supplies 3.3V power to the
OSC and to the internal regulator that in turn supplies the Phase
Locked Loop. It must be connected to a clean analog power
supply.



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