56F8167 datasheet(61/184 Pages) FREESCALE

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Peripheral Memory Mapped Registers

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Table 4-19 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

Address Offset

IPR 0

Interrupt Priority Register 0

IPR 1

Interrupt Priority Register 1

IPR 2

Interrupt Priority Register 2

IPR 3

Interrupt Priority Register 3

IPR 4

Interrupt Priority Register 4

IPR 5

Interrupt Priority Register 5

IPR 6

Interrupt Priority Register 6

IPR 7

Interrupt Priority Register 7

IPR 8

Interrupt Priority Register 8

IPR 9

Interrupt Priority Register 9

VBA

Vector Base Address Register

FIM0

Fast Interrupt Match Register 0

FIVAL0

Fast Interrupt Vector Address Low 0 Register

FIVAH0

Fast Interrupt Vector Address High 0 Register

FIM1

Fast Interrupt Match Register 1

FIVAL1

Fast Interrupt Vector Address Low 1 Register

FIVAH1

$10

Fast Interrupt Vector Address High 1 Register

IRQP 0

$11

IRQ Pending Register 0

IRQP 1

$12

IRQ Pending Register 1

IRQP 2

$13

IRQ Pending Register 2

IRQP 3

$14

IRQ Pending Register 3

IRQP 4

$15

IRQ Pending Register 4

IRQP 5

$16

IRQ Pending Register 5

Reserved

ICTL

$1D

Interrupt Control Register

Reserved

IPR10

$1F

Interrupt Priority Register 10

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