56F8167 datasheet(67/184 Pages) FREESCALE

67 / 184 page

Peripheral Memory Mapped Registers

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Table 4-30 GPIOB Registers Address Map

(GPIOB_BASE = $00 F300)

Address Offset

Reset Value

GPIOB_PUR

Pull-up Enable Register

0 x 00FF

GPIOB_DR

Data Register

0 x 0000

GPIOB_DDR

Data Direction Register

0 x 0000

GPIOB_PER

Peripheral Enable Register

0 x 000F for 20-bit EMI

address at reset.

0 x 0000 for all other cases.

See Table 4-4 for details.

GPIOB_IAR

Interrupt Assert Register

0 x 0000

GPIOB_IENR

Interrupt Enable Register

0 x 0000

GPIOB_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOB_IPR

Interrupt Pending Register

0 x 0000

GPIOB_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOB_PPMODE

Push-Pull Mode Register

0 x 0000

GPIOB_RAWDATA

Raw Data Input Register

—

Table 4-31 GPIOC Registers Address Map

(GPIOC_BASE = $00F310)

Address Offset

Reset Value

GPIOC_PUR

Pull-up Enable Register

0 x 07FF

GPIOC_DR

Data Register

0 x 0000

GPIOC_DDR

Data Direction Register

0 x 0000

GPIOC_PER

Peripheral Enable Register

0 x 07FF

GPIOC_IAR

Interrupt Assert Register

0 x 0000

GPIOC_IENR

Interrupt Enable Register

0 x 0000

GPIOC_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOC_IPR

Interrupt Pending Register

0 x 0000

GPIOC_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOC_PPMODE

Push-Pull Mode Register

0 x 07FF

GPIOC_RAWDATA

Raw Data Input Register

—

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