56F8167 datasheet(22/184 Pages) FREESCALE

22 / 184 page

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

GPIOB0

(A16)

Schmitt

Input/

Output

Input,

pull-up

enabled

Port B GPIO — These four GPIO pins can be programmed as

input or output pins.

Address Bus — A16 - A19 specify one of the address lines for

external program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

when the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

After reset, the startup state of GPIOB0 - GPIOB3 (GPIO or

address) is determined as a function of EXTBOOT, EMI_MODE

and the Flash security setting. See Table 4-4 for further

information on when this pin is configured as an address pin at

reset. In all cases, this state may be changed by writing to

GPIOB_PER.

To deactivate the internal pull-up resistor, clear the appropriate

GPIO bit in the GPIOB_PUR register.

GPIOB1

(A17)

GPIOB2

(A18)

GPIOB3

(A19)

GPIOB4

(A20)

(prescaler_

clock)

Schmitt

Input/

Output

Input,

pull-up

enabled

Port B GPIO — These four GPIO pins can be programmed as

input or output pins.

Address Bus — A20 - A23 specify one of the address lines for

external program or data memory accesses.

Depending upon the state of the DRV bit in the EMI bus control

the external bus is inactive.

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

Clock Outputs — can be used to monitor the prescaler_clock,

SYS_CLK, SYS_CLK2 or oscillator_clock on GPIOB4 through

GPIOB7, respectively.

After reset, the default state is GPIO.

These pins can also be used to extend the external address bus

to its full length or to view any of several system clocks. In these

cases, the GPIO_B_PER can be used to individually disable the

GPIO. The CLKOSR register in the SIM (see Part 6.5.7) can then

be used to choose between address and clock functions.

GPIOB5

(A21)

(SYS_CLK)

GPIOB6

(A22)

(SYS_CLK2)

GPIOB7

(A23)

(oscillator_

clock)

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

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