56F8167 datasheet(25/184 Pages) FREESCALE

25 / 184 page

Signal Pins

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Output

In reset,

output is

disabled,

pull-up is

enabled

Write Enable — WR is asserted during external memory write

cycles. When WR is asserted low, pins D0 - D15 become outputs

and the device puts data on the bus. When WR is deasserted

high, the external data is latched inside the external device. When

WR is asserted, it qualifies the A0 - A23, PS, DS, and CSn pins.

WR can be connected directly to the WE pin of a static RAM.

Depending upon the state of the DRV bit in the EMI bus control

Most designs will want to change the DRV state to DRV = 1 instead

of using the default setting.

To deactivate the internal pull-up resistor, set the CTRL bit in the

SIM_PUDR register.

(CS0)

(GPIOD8)

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Program Memory Select — This signal is actually CS0 in the

EMI, which is programmed at reset for compatibility with the

56F80x PS signal. PS is asserted low for external program

memory access.

Depending upon the state of the DRV bit in the EMI bus control

CS0 resets to provide the PS function as defined on the 56F80x

devices.

Port D GPIO — This GPIO pin can be individually programmed

as an input or output pin.

To deactivate the internal pull-up resistor, clear bit 8 in the

GPIOD_PUR register.

(CS1)

(GPIOD9)

Output

Input/

Output

In reset,

output is

disabled,

pull-up is

enabled

Data Memory Select — This signal is actually CS1 in the EMI,

which is programmed at reset for compatibility with the 56F80x

DS signal. DS is asserted low for external data memory access.

Depending upon the state of the DRV bit in the EMI bus control

CS1 resets to provide the DS function as defined on the 56F80x

devices.

Port D GPIO — This GPIO pin can be individually programmed

as an input or output pin.

To deactivate the internal pull-up resistor, clear bit 9 in the

GPIOD_PUR register.

Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA

Signal

Name

No.

Ball No.

Type

State

During

Reset

Signal Description

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