56F8167 datasheet(62/184 Pages) FREESCALE

62 / 184 page

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Table 4-20 Analog-to-Digital Converter Registers Address Map

(ADCA_BASE = $00 F200)

Address Offset

ADCA_CR 1

Control Register 1

ADCA_CR 2

Control Register 2

ADCA_ZCC

Zero Crossing Control Register

ADCA_LST 1

Channel List Register 1

ADCA_LST 2

Channel List Register 2

ADCA_SDIS

Sample Disable Register

ADCA_STAT

Status Register

ADCA_LSTAT

Limit Status Register

ADCA_ZCSTAT

Zero Crossing Status Register

ADCA_RSLT 0

Result Register 0

ADCA_RSLT 1

Result Register 1

ADCA_RSLT 2

Result Register 2

ADCA_RSLT 3

Result Register 3

ADCA_RSLT 4

Result Register 4

ADCA_RSLT 5

Result Register 5

ADCA_RSLT 6

Result Register 6

ADCA_RSLT 7

$10

Result Register 7

ADCA_LLMT 0

$11

Low Limit Register 0

ADCA_LLMT 1

$12

Low Limit Register 1

ADCA_LLMT 2

$13

Low Limit Register 2

ADCA_LLMT 3

$14

Low Limit Register 3

ADCA_LLMT 4

$15

Low Limit Register 4

ADCA_LLMT 5

$16

Low Limit Register 5

ADCA_LLMT 6

$17

Low Limit Register 6

ADCA_LLMT 7

$18

Low Limit Register 7

ADCA_HLMT 0

$19

High Limit Register 0

ADCA_HLMT 1

$1A

High Limit Register 1

ADCA_HLMT 2

$1B

High Limit Register 2

ADCA_HLMT 3

$1C

High Limit Register 3

ADCA_HLMT 4

$1D

High Limit Register 4

ADCA_HLMT 5

$1E

High Limit Register 5

ADCA_HLMT 6

$1F

High Limit Register 6

ADCA_HLMT 7

$20

High Limit Register 7

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