56F8167 datasheet(65/184 Pages) FREESCALE

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Peripheral Memory Mapped Registers

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Table 4-23 Serial Communication Interface 0 Registers Address Map

(SCI0_BASE = $00 F280)

Address Offset

SCI0_SCIBR

Baud Rate Register

SCI0_SCICR

Control Register

Reserved

SCI0_SCISR

Status Register

SCI0_SCIDR

Data Register

Table 4-24 Serial Communication Interface 1 Registers Address Map

(SCI1_BASE = $00 F290)

Address Offset

SCI1_SCIBR

Baud Rate Register

SCI1_SCICR

Control Register

Reserved

SCI1_SCISR

Status Register

SCI1_SCIDR

Data Register

Table 4-25 Serial Peripheral Interface 0 Registers Address Map

(SPI0_BASE = $00 F2A0)

Address Offset

SPI0_SPSCR

Status and Control Register

SPI0_SPDSR

Data Size Register

SPI0_SPDRR

Data Receive Register

SPI0_SPDTR

Data Transmitter Register

Table 4-26 Serial Peripheral Interface 1 Registers Address Map

(SPI1_BASE = $00 F2B0)

Address Offset

SPI1_SPSCR

Status and Control Register

SPI1_SPDSR

Data Size Register

SPI1_SPDRR

Data Receive Register

SPI1_SPDTR

Data Transmitter Register

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