56F8167 datasheet(69/184 Pages) FREESCALE

69 / 184 page

Peripheral Memory Mapped Registers

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

Preliminary

Table 4-34 GPIOF Registers Address Map

(GPIOF_BASE = $00 F340)

Address Offset

Reset Value

GPIOF_PUR

Pull-up Enable Register

0 x FFFF

GPIOF_DR

Data Register

0 x 0000

GPIOF_DDR

Data Direction Register

0 x 0000

GPIOF_PER

Peripheral Enable Register

0 x FFFF

GPIOF_IAR

Interrupt Assert Register

0 x 0000

GPIOF_IENR

Interrupt Enable Register

0 x 0000

GPIOF_IPOLR

Interrupt Polarity Register

0 x 0000

GPIOF_IPR

Interrupt Pending Register

0 x 0000

GPIOF_IESR

Interrupt Edge-Sensitive Register

0 x 0000

GPIOF_PPMODE

Push-Pull Mode Register

0 x FFFF

GPIOF_RAWDATA

Raw Data Input Register

—

Table 4-35 System Integration Module Registers Address Map

(SIM_BASE = $00 F350)

Address Offset

SIM_CONTROL

Control Register

SIM_RSTSTS

Reset Status Register

SIM_SCR0

Software Control Register 0

SIM_SCR1

Software Control Register 1

SIM_SCR2

Software Control Register 2

SIM_SCR3

Software Control Register 3

SIM_MSH_ID

Most Significant Half JTAG ID

SIM_LSH_ID

Least Significant Half JTAG ID

SIM_PUDR

Pull-up Disable Register

Reserved

SIM_CLKOSR

Clock Out Select Register

SIM_GPS

Quad Decoder 1 / Timer B / SPI 1 Select Register

SIM_PCE

Peripheral Clock Enable Register

SIM_ISALH

I/O Short Address Location High Register

SIM_ISALL

I/O Short Address Location Low Register

SIM_PCE2

Peripheral Clock Enable Register 2

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