56F8167 datasheet(107/184 Pages) FREESCALE

107 / 184 page

56F8367 Technical Data, Rev. 7.0

Freescale Semiconductor

107

Preliminary

5.6.23.2

IRQ Pending (PENDING)—Bits 81–85

This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2

through 85.

•

0 = IRQ pending for this vector number

•

1 = No IRQ pending for this vector number

5.6.24

Reserved—Base + 17

5.6.25

Reserved—Base + 18

5.6.26

Reserved—Base + 19

5.6.27

Reserved—Base + 1A

5.6.28

Reserved—Base + 1B

5.6.29

Reserved—Base + 1C

5.6.30

ITCN Control Register (ICTL)

Figure 5-26 ITCN Control Register (ICTL)

5.6.30.1

Interrupt (INT)—Bit 15

This read-only bit reflects the state of the interrupt to the 56800E core.

•

0 = No interrupt is being sent to the 56800E core

•

1 = An interrupt is being sent to the 56800E core

5.6.30.2

Interrupt Priority Level (IPIC)—Bits 14–13

These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E

core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to a new

interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt service routine can

read it.

•

00 = Required nested exception priority levels are 0, 1, 2, or 3

•

01 = Required nested exception priority levels are 1, 2, or 3

•

10 = Required nested exception priority levels are 2 or 3

•

11 = Required nested exception priority level is 3

Base + $1D

Read

INT

IPIC

VAB

INT_DIS

IRQB STATE

IRQA STATE

IRQB

EDG

IRQA

EDG

Write

RESET

000

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