DSP56857 datasheet(187/662 Pages) FREESCALE

187 / 662 page

Overview, Rev. 4

Freescale Semiconductor

8-9

8.7.2 Interrupt Priority Register 1 (IPR1)

Figure 8-4. Interrupt Priority Register 1 (IPR1)

See Programmer’s Sheet on Appendix page B - 22

8.7.2.1 Reserved—Bits 15–6

These bits are reserved or not implemented. They are read as 0, but they cannot be modified by

writing.

8.7.2.2 EOnCE Receive Register Empty Interrupt Priority Level

(RX_REG IPL)—Bits 5–4

This bit field is used to set the interrupt priority levels for certain EOnCE IRQs. These IRQs are

limited to priorities one through three and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

8.7.2.3 EOnCE Transmit Register Full Interrupt Priority Level

(TX_REG IPL)—Bits 3–2

This bit field is used to set the interrupt priority levels for certain EOnCE IRQs. These IRQs are

limited to priorities one through three and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

8.7.2.4 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—Bits 1–0

This bit field is used to set the interrupt priority levels for certain EOnCE IRQs. These IRQs are

limited to priorities one through three and are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

Base + $1

Read

RX_REG IPL

TX_REG IPL

TRBUF IPL

Write

Reset

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