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DSP56857 bảng dữ liệu(PDF) 186 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 186 Page - Freescale Semiconductor, Inc |
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186 / 662 page ![]() Register Descriptions (ITCN_BASE = $1FFF20) 5685X Digital Signal Controller User Manual, Rev. 4 8-8 Freescale Semiconductor 8.7 Register Descriptions (ITCN_BASE = $1FFF20) 8.7.1 Interrupt Priority Register 0 (IPR0) Figure 8-3. Interrupt Priority Register 0 (IPR0) See Programmer’s Sheet on Appendix page B - 21 8.7.1.1 Reserved—Bits 15–14 These bits are reserved or not implemented. They are read as 0, but they cannot be modified by writing. 8.7.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL)—Bits 13–12 This bit field is used to set the interrupt priority levels for certain EOnCE IRQs. These IRQs are limited to priorities one through three and are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 8.7.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL)—Bits 11–10 This bit field is used to set the interrupt priority levels for certain EOnCE IRQs. These IRQs are limited to priorities one through three and are disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 8.7.1.4 Reserved—Bits 9–0 These bits are reserved or not implemented. They are read as 0, but they cannot be modified by writing. Base + $0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 BKPT_U0 IPL STPCNT IPL 0 0 0 0 0 0 0 0 0 0 Write Reset 0 0 0 0 0 0 0 0 00 000 00 0 |
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