DSP56857 datasheet(531/662 Pages) FREESCALE

531 / 662 page

Application:

Date:

Programmer:

Sheet

Appendix B - Programmer’s Sheets, Rev. 4

Freescale Semiconductor

B-29

9 of 24

ITCN

Interrupt Priority Register 5 (IPR5)

Bits

Name

Description

15 - 14

HOST_XMIT IPL

SCI Receive Full Interrupt Priority Level

This bit field is used to set the interrupt priority levels for this peripheral IRQ.

IRQ disabled by default

IRQ is priority level 0

IRQ is priority level 1

IRQ is priority level 2

13 - 12

HOST_RCV IPL

SCI Receive Error Interrupt Priority Level

This bit field is used to set the interrupt priority levels for this peripheral IRQ.

IRQ disabled by default

IRQ is priority level 0

IRQ is priority level 1

IRQ is priority level 2

11 - 10

SCI0_RCV IPL

SCI Receive Idle Interrupt Priority Level

This bit field is used to set the interrupt priority levels for this peripheral IRQ.

IRQ disabled by default

IRQ is priority level 0

IRQ is priority level 1

IRQ is priority level 2

9 - 8

SCI0_RERR IPL

SCI0 Transmitter Idle Interrupt Priority Level

This bit field is used to set the interrupt priority levels for certain peripheral IRQs.

IRQ disabled by default

IRQ is priority level 0

IRQ is priority level 1

IRQ is priority level 2

Interrupt Priority

$1FFF20 + $5

Bits

Read HOST_XMIT

IPL

HOST_RCV

IPL

SCI0_RCV

IPL

SCI0_RERR

IPL

SC0_RIDL

IPL

SCI0_TDL

IPL

SCI0_XMIT

IPL

SPI_XMIT

IPL

Write

Reset

000

0000

00000

0000

See the following page for continuation of this register

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