DSP56857 datasheet(281/662 Pages) FREESCALE

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Transmission Formats

Serial Peripheral Interface (SPI), Rev. 4

Freescale Semiconductor

11-11

11.7.1 Data Transmission Length

The SPI can support data lengths from one to 16 bits. This can be configured in the Data Size

the upper bits with zeros. It is the responsibility of the software to remove these upper bits since

16 bits will be read when reading the Receive Data register (SPDRR).

Note:

Data can be lost if the data length is not the same for both master and slave devices.

11.7.2 Data Shift Ordering

The SPI can be configured to transmit or receive the MSB of the desired data first or last. This is

controlled by the Data Shift Order (DSO) bit in the SPSCR. Regardless which bit is transmitted

or received first, the data shall always be written to the SPI Data Transmit Register (SPDTR) and

read from the Receive Data Register (SPDRR) with the LSB in bit 0 and the MSB in the correct

position, depending on the data transmission size.

11.7.3 Clock Phase and Polarity Controls

Software can select any of four combinations of Serial Clock (SCLK) phase and polarity using

two bits in the SPI Status and Control Register (SPSCR). The Clock Polarity is specified by the

(CPOL) control bit. In turn, it selects an active high or low clock. It has no significant effect on

the transmission format.

The Clock Phase (CPHA) control bit selects one of two fundamentally different transmission

formats. The clock phase and polarity should be identical for the master SPI device and the

communicating slave device. In some cases, the phase and polarity are changed between

transmissions, allowing a master device to communicate with peripheral slaves with different

requirements.

Note:

Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI

Enable (SPE) bit. Do not change SPE and CPHA or CPOL at the same time.

11.7.4 Transmission Format When CPHA = 0

Figure 11-6 exhibits a SPI transmission with CPHA as Logic 0. The figure should not be used as

a replacement for data sheet parametric information. Two waveforms are shown for SCLK:

1. CPOL = 0

2. CPOL = 1

The diagram may be interpreted as a master or slave timing diagram since the Serial Clock

(SCLK), Master In/Slave Out (MISO), and Master Out/Slave In (MOSI) pins are directly

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