DSP56857 datasheet(284/662 Pages) FREESCALE

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Transmission Formats

5685X Digital Signal Controller User Manual, Rev. 4

11-14

Freescale Semiconductor

When CPHA = 1 for a slave, the first edge of the SCLK indicates the beginning of the

transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the

first bit of its data. Once the transmission begins, no new data is allowed into the Shift Register

from the Data Transmit Register. Therefore, the SPI Data Register of the slave must be loaded

with transmit data before the first edge of SCLK. Any data written after the first edge is stored in

the Data Transmit Register and transferred to the Shift Register after the current transmission.

11.7.6 Transmission Initiation Latency

When the SPI is configured as a master (SPMSTR = 1), writing to the SPDTR starts a

transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect

the initial state of the SCLK signal. When CPHA = 0, the SCLK signal remains inactive for the

first half of the first SCLK cycle. When CPHA = 1, the first SCLK cycle begins with an edge on

the SCLK line from its inactive to its active level. The SPI clock rate, selected by SPR1:SPR0,

affects the delay from the write to SPDTR and the start of the SPI transmission. The internal SPI

clock in the master is a free-running derivative of the internal clock. To conserve power, it is

enabled only when both the SPE and SPMSTR bits are set. Since the SPI clock is free-running, it

is uncertain where the write to the SPDTR occurs relative to the slower SCLK. This uncertainty

causes the variation in the initiation delay, demonstrated in Figure 11-9. This delay is no longer

than a single SPI bit time. That is, the maximum delay is two bus cycles for DIV2, four bus

cycles for DIV4, eight bus cycles for DIV8, and so on up to a maximum of 256 cycles for

DIV256.

Note:

Figure 11-9 assumes 16-bit data lengths and the MSB shifted out first.

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